2-lane MIPI MCLK/PWDN configuration

Hello everyone,

On the Jetson Nano configuration, CAM0_PWDN(114), CAM0_MCLK(116) are assigned to CAM0 and CAM1_PWDN(120), CAM1_MCLK(122) are assigned to CAM1, Does anyone know how can I change the configuration the way like this CAM0_PWDN(114), CAM0_MCLK(116) go CAM1, CAM1_PWDN(120), CAM1_MCLK(122) go CAM0?


hello zheng1,

may I know what’s the actual use-case?
Jetson Nano brings twelve MIPI CSI lanes to the connector,
please refer to Jetson Nano Product Design Guide, you should see [Table 8-3. CSI Configuration] for more details.

In the carrier board P3449 B01 design, 114&116 are assigned to the CSI-0 2-Lane interface; 120&122 are assigned to the CSI-2. When it comes to the 4-Lane design The CSI-AB(CSI 0&1) interface is configured with CAM1_PWDN(120), CAM1_MCLK(122), while the CSI-CD(CSI4) interface is configured with CAM0_PWDN(114), CAM0_MCLK(116).
So, I am thinking of if the MCLK/PWDN configuration would be fixed once any 2/4-Lane mode is initiated or could be switched by the user.

One of my cases is we have a camera sensor module that does not have MCLK/PWDN interface or I2C interface. the sensor register configuration interface is SPI. So, how can configure it on the Jetson Nano side?

hello zheng1,

you may check this kernel driver for using SPI interface.
i.e. $L4T_Sources/r32.6.1/Linux_for_Tegra/source/public/kernel/nvidia/drivers/media/spi/imx204.c