2 USB 3.0 Host post issue

Hi all,

In our custom board we have 2 USB 3.0 host ports. Out of two ports one is working in 3.0 and another at 2.0. I have made all the changes that have mentioned in the forum link “https://devtalk.nvidia.com/default/topic/892568/?comment=4728998” (in extlinux.conf, dts and machine file), but the issue remains same. Are we missing something here?

Thanks in advance

There is only one USB3 controller. See chapter 19 (section 19.1) of the TRM:
https://developer.nvidia.com/embedded/dlc/tegra-x1-technical-reference-manual

we refer the design guide and it seems that 2 USB 3.0 is possible. Kindly refer page 42 in the design guide “TegraK1_Embedded_DG_v03.pdf”.

Are we missing something or is there any confusion between design guide and the TRM?

It looks like a single XUSB 3.0 controller works on up to two separate ports, which I had not previously noticed. XUSB 3.0 would first require assigning two USB2 controllers to the XUSB 3.0 controller (via PADCTL); following this actual ports could then be assigned to the XUSB 3.0 controller (TRM section 19.6). However, I don’t see an example of two XUSB 3.0 ports. I get the feeling that it’s critical to assign two USB2 controllers to the XUSB 3.0 controller prior to any XUSB 3.0 setup (exactly what is required for kernel parameters to do this I do not know).

"Are we missing something or is there any confusion between design guide and the TRM? "
Yes

“It looks like a single XUSB 3.0 controller works on up to two separate ports”
Yes but there is still ONLY ONE USB3 controller.

The idea is that the USB3 controller can be used on either port.
Not sure what is going to happen if the same controlled is routed to 2 ports at the same time.

What happens if the same controller has to talk to 2 USB3 devices on both ports (think about simultaneous access)?

I’m just wondering if perhaps the USB3 controller is able to act as a root HUB (the design guide tends to indicate this…one has to read between the lines in the TRM to verify). There would be bandwidth concerns sharing USB3, but if bandwidth is sufficient it might save costs on hardware (just like any other HUB, but internal without added components).

I will again go through the design guide and the TRM.

From the forum I found few are trying the same and they had similar issues. Kindly refer the below link

https://devtalk.nvidia.com/default/topic/892568/?comment=4728998

https://devtalk.nvidia.com/default/topic/899009/embedded-systems/software-configuration-for-tegra-k1-with-additional-usb3-0-port/

But none of them came back. I don’t know if they solved the issue.

Hi Jeslin,

TK1 does support 2 USB3.0 ports which share total 5Gbps bandwith. Could you pls share the USB connections part schematic of this custom board so as to eliminate HW issue ?