3.3V fall time slowly

Autonomous Machines Jetson & Embedded Systems Jetson Xavier NX
1

Hi,

Design Guide point out SYS_RESET* ramped to VDD_3V3_SYS fall of ramped Max is 1.5ms.
I measure reference board, it very close 1.5ms.

3.3V of Reference design supply to M.2 M-key and E-key.
In our design, we have more M.2 device than reference board, so it need more capacity on device.
However, more capacity cause 3.3V fall time slowly. It about 9ms.
Is it have any impact or side effect in this design? Or do you have any suggestion?

Thanks,
Allison

3

Please list in which sequence of which doc that you are talking about. I am not sure what you mean the timing. Is it power on or power off? The key point is to let carrier rails off earlier than module. You can probe the M.2 device pins voltage level and module power to make sure the pins is off earlier than module power.

4

Hi Trumany,

I means this timing:

image
image1014×426 29.1 KB

It only shows 3.3V on Carrier Board power down time need under 1.5mS after SYS_RESET* .

This timing in our board is 8ms, is it have any side effect on borad?

5

It might be risk if violating the spec. You should try to fix it as far as possible. Or you can probe the real timing between carrier supplies and module power on your board to make sure carrier is off earlier than module.

6

Hi Trumany,

We wnat to know what value of Vl, the red mark of below picture.
Is 30% or 20% or 10%?

image
image962×403 29.3 KB

Thanks,
Allison

7

Generally for CMOS pin, VIL is 0.25 x VDD.

8

Hi Trumany,

Thanks for your answer.
And we are under testing now, could you don’t close this discussion thread now?
Your suggestion is good for me.
But I need some time to test it more, and I will updated my test result to you.
If I have any question, I can asking you in this discussion thread until I resolved it.

Thanks,
Allison

9

Hi Trumany,

You said that carrier board’s power is off earlier than module power.
Could you point out what exactly “module power” ?
Which one is true?

  1. module power = VDD_IN on SOM(pin251~pin260)
  2. module power down = SYS_RST* down
    Sorry, I just want to clarify this question.

Thanks,
Allison

10

No need to care about module internal power rails. The carrier power rails only need to be off following the power down sequence as the timing range to SYS_RESET.

11

Hi Trumany,

I understand. I’ll follow your suggestion.

Thanks,
Allison

13

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