4 questions about Fermi GPU
1 In each SM, where does the â€œcontext of blocksâ€ storeï¼ŸIn register or shared or caches ? If in caches, which caches ?
2 what is the MaxBlocksPerSM for Fermiï¼Ÿ Is it 8?
3 for all kinds of caches (global cache, local cache, L1 cache, L2 cache, constant cache, uniform cache, texture cache, instruction cache), Where are their exact positions in chip? (I only find instruction cache and L2Cache on publications)
L1 cache = uniform cache + instruction cache ? L2 cache = textcache + constant cache ?
their relationships? Their capacity? Their functions?
4 where can I find the table for Fermi instructionsâ€™ IPC (instruction per clock) ?