40-bit address space on CUDA enabled devices

In http://docs.nvidia.com/cuda/pdf/CUDA_C_Programming_Guide.pdf page 21 it says,

“Linear memory exists on the device in a 32-bit address space for devices of compute capability 1.x and 40-bit address space of devices of higher compute capability, so separately allocated entities can reference one another via pointers, for example, in a binary tree.”

What does it mean by

“separately allocated entities can reference one another via pointers” ?