64b Single-Channel supports?

Autonomous Machines Jetson & Embedded Systems Jetson TX1
1

Hi, Guys.

I’d like to limit LPDDR4 memory channel area.

Regarding to TRM, TegraX1 seems to support 32b Dual-Channel only.

Is there any way to use 64b Single-Channel?

Thanks

2

Please have a try…
Set the “dram_x64 : 0” in PAR file in stead of “dram_x64 : 1” then transfer the par to cfg file.
64bit:
SDRAM[0].EmcCfg3 = 0x00000040;
SDRAM[0].McEmemCfg = 0x00001000;

32bit:
SDRAM[0].EmcCfg3 = 0x00000000;
SDRAM[0].McEmemCfg = 0x00000400;

Set the “num_ch : 1” in PAR file in stead of “num_ch : 2” then transfer the par to cfg file.

Single channel(32bit):
SDRAM[0].McEmemAdrCfgChannelMask = 0x00000000;
SDRAM[0].McEmemAdrCfgBankMask0 = 0xeb772400;
SDRAM[0].McEmemAdrCfgBankMask1 = 0x249e4800;
SDRAM[0].McEmemAdrCfgBankMask2 = 0x5dbbb000;
SDRAM[0].McEmemCfg = 0x00000800;
SDRAM[0].McEmemArbOutstandingReq = 0x80000040;
SDRAM[0].EmcPmcScratch1 = 0x4301f3ff;
SDRAM[0].PmcIoDpd3Req = 0x4301f3ff;
SDRAM[0].EmcFbioCfg7 = 0x00003bfb;
SDRAM[0].ClearClk2Mc1 = 0x00000001;
SDRAM[0].EmcBctSpare9 = 0x30000000;

Dual channel(64bit):
SDRAM[0].McEmemAdrCfgChannelMask = 0xffff2400;
SDRAM[0].McEmemAdrCfgBankMask0 = 0x6e574400;
SDRAM[0].McEmemAdrCfgBankMask1 = 0x39722800;
SDRAM[0].McEmemAdrCfgBankMask2 = 0x4b9c1000;
SDRAM[0].McEmemCfg = 0x00001000;
SDRAM[0].McEmemArbOutstandingReq = 0x80000080;
SDRAM[0].EmcPmcScratch1 = 0x4f01ffff;
SDRAM[0].PmcIoDpd3Req = 0x4f01ffff;
SDRAM[0].EmcFbioCfg7 = 0x00003bff;
SDRAM[0].ClearClk2Mc1 = 0x00000000;
SDRAM[0].EmcBctSpare9 = 0x00000000;

3

Thank you edli1983

It would be very helpful information for me.
I have a question.

Do you have any plans to release Memory Characterization Tool for TegraX1?

4

No, NV has no plan to release the memory characterization tool for Jetson TX1.
Jetson TX1 module has been qualified with the on-board config already.

5

Ok, I see. Thank you.