8-lane CSI gang mode

Hi, I am trying to get my 8-lane CSI camera working.

It works on the Jetson Nano. I ported the device tree to TX2 NX (same sensor mode settings, active_w, active_h, pixel_phase, csi_pixel_bit_depth, line_length, pix_clk_hz).

Camera is connected to CSI_2, CSI_3, and CSI_4 for both NANO and TX2 NX. tegra_sinterface = serial_c, port-index = <2>, bus-width = <8>. I don’t think this should be changed. Image looks good on NANO, but because CSI_C/CSI_D and CSI_E/CSI_F are swapped for TX2, I changed CAMERA_GANG_L_R to CAMERA_GANG_R_L (though I tested both).

I test with the following pipeline, which works on the NANO:

gst-launch-1.0 v4l2src ! video/x-raw,width=3840,height=2160 ! nvvidconv ! nvv4l2h264enc ! h264parse ! qtmux ! filesink location=/tmp/test.mp4 -e

Setting pipeline to PAUSED …
Opening in BLOCKING MODE
Pipeline is live and does not need PREROLL …
Setting pipeline to PLAYING …
New clock: GstSystemClock
Redistribute latency…
NvMMLiteOpen : Block : BlockType = 4
===== NVMEDIA: NVENC =====
NvMMLiteBlockCreate : Block : BlockType = 4
[ 102.701175] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 102.707579] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 102.717479] nvcsi 150c0000.nvcsi: csi4_stream_check_status (2) ERROR_STATUS2VI_VC0 = 0x0000000e
[ 102.726235] nvcsi 150c0000.nvcsi: csi4_stream_check_status (2) INTR_STATUS 0x0001000e
[ 102.734075] nvcsi 150c0000.nvcsi: csi4_stream_check_status (2) ERR_INTR_STATUS 0x0001000e
[ 102.742318] nvcsi 150c0000.nvcsi: csi4_stream_check_status (4) ERROR_STATUS2VI_VC0 = 0x00000006
[ 102.751029] nvcsi 150c0000.nvcsi: csi4_stream_check_status (4) INTR_STATUS 0x0001000e
[ 102.758865] nvcsi 150c0000.nvcsi: csi4_stream_check_status (4) ERR_INTR_STATUS 0x0001000e
[ 103.033314] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 103.039765] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 103.049979] nvcsi 150c0000.nvcsi: csi4_stream_check_status (2) ERROR_STATUS2VI_VC0 = 0x0000000e
[ 103.058745] nvcsi 150c0000.nvcsi: csi4_stream_check_status (2) INTR_STATUS 0x0001000c
[ 103.066609] nvcsi 150c0000.nvcsi: csi4_stream_check_status (2) ERR_INTR_STATUS 0x0001000c
[ 103.074936] nvcsi 150c0000.nvcsi: csi4_stream_check_status (4) ERROR_STATUS2VI_VC0 = 0x0000000e
[ 103.083735] nvcsi 150c0000.nvcsi: csi4_stream_check_status (4) INTR_STATUS 0x0001000e
[ 103.091653] nvcsi 150c0000.nvcsi: csi4_stream_check_status (4) ERR_INTR_STATUS 0x0001000e
[ 103.333340] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 103.339847] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 103.349843] nvcsi 150c0000.nvcsi: csi4_stream_check_status (2) ERROR_STATUS2VI_VC0 = 0x0000000e
[ 103.358598] nvcsi 150c0000.nvcsi: csi4_stream_check_status (2) INTR_STATUS 0x0001000e
[ 103.366452] nvcsi 150c0000.nvcsi: csi4_stream_check_status (2) ERR_INTR_STATUS 0x0001000e
[ 103.374697] nvcsi 150c0000.nvcsi: csi4_stream_check_status (4) ERROR_STATUS2VI_VC0 = 0x0000000e
[ 103.383409] nvcsi 150c0000.nvcsi: csi4_stream_check_status (4) INTR_STATUS 0x0001000e
[ 103.391322] nvcsi 150c0000.nvcsi: csi4_stream_check_status (4) ERR_INTR_STATUS 0x0001000e
^Chandling interrupt.
Interrupt: Stopping pipeline …
EOS on shutdown enabled – Forcing EOS on the pipeline
Waiting for EOS…
Got EOS from element “pipeline0”.
EOS received - stopping pipeline…
Execution ended after 0:00:01.150279293
Setting pipeline to PAUSED …
Setting pipeline to READY …
[ 103.669411] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 103.675791] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 103.685585] nvcsi 150c0000.nvcsi: csi4_stream_check_status (2) ERROR_STATUS2VI_VC0 = 0x0000000e
[ 103.694307] nvcsi 150c0000.nvcsi: csi4_stream_check_status (2) INTR_STATUS 0x0001000e
[ 103.702190] nvcsi 150c0000.nvcsi: csi4_stream_check_status (2) ERR_INTR_STATUS 0x0001000e
[ 103.710523] nvcsi 150c0000.nvcsi: csi4_stream_check_status (4) ERROR_STATUS2VI_VC0 = 0x0000000e
[ 103.719297] nvcsi 150c0000.nvcsi: csi4_stream_check_status (4) INTR_STATUS 0x0001000e
[ 103.727216] nvcsi 150c0000.nvcsi: csi4_stream_check_status (4) ERR_INTR_STATUS 0x0001000e
[ 103.736219] nvcsi 150c0000.nvcsi: csi4_stream_check_status (2) ERROR_STATUS2VI_VC0 = 0x0000000e
[ 103.745062] nvcsi 150c0000.nvcsi: csi4_stream_check_status (2) INTR_STATUS 0x0000000c
[ 103.753021] nvcsi 150c0000.nvcsi: csi4_stream_check_status (2) ERR_INTR_STATUS 0x0000000c
[ 103.761263] nvcsi 150c0000.nvcsi: csi4_stream_check_status (4) ERROR_STATUS2VI_VC0 = 0x0000000e
[ 103.770064] nvcsi 150c0000.nvcsi: csi4_stream_check_status (4) INTR_STATUS 0x00000004
[ 103.777984] nvcsi 150c0000.nvcsi: csi4_stream_check_status (4) ERR_INTR_STATUS 0x00000004
Setting pipeline to NULL …
Freeing pipeline …

I read here Jetson TX2 NX PXL_SOF - #5 by ShaneCCC

Due to TX2 will check the sensor output lines and frames must to match the report size but Nano didn’t do the checked that is why if you driver report more or less few lines/frames that wouldn’t have problem on Nano. However TX2 will check if less or more will alert error. Also the active image dimension may not always the same with the output lines/frames that’s why I said it depend on sensor. Usually it maybe few lines/frames than the active dimensions.

How can I disable this check?

I also tried boosting vi clock.

What else can I try?

Sorry to tell can’t disable this checking.

Thanks

Could you confirm by two 4 lane instead of gain mode.

I just tried single 4 lane half width capture on TX2. It does not work.
I will try this on the Nano but will take some time.

I have solved the timing issue. Thank you for your support.

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