8TB Sabrent Drive not recognized on Jetpack 4.4

We have recently tested a Sabrent 8TB NVME SSD on two of our Xavier AGX dev kits. One is running Jetpack 4.2.3 and one running Jetpack 4.4.

We have had success with a samsung evo 970 1TB NVME SSD in both devkits, but the Sabrent drive is not recognized in the Jetpack 4.4 box. It doesn’t show up in lspci, lsblk or in any dmesg logs.

Any ideas on what may be going wrong in 4.4 would be most helpful.

See

for where we started.

Hi,

Could you share the dmesg when you connect the Sabrent SSD?

Here you go. The drive was in and this is the dmesg from boot up.

dmesg.log (78.8 KB)

we used to test Sabrient Rocket PCIe gen 4. of smaller size 0,5 Gb The issue was that it is a two sided nvme thus it has to curve / deform in order to fit into Jetson M,2 slot and get screwed by bolt

Could you please try with the below patch and update your observations?

diff --git a/drivers/pci/dwc/pcie-tegra.c b/drivers/pci/dwc/pcie-tegra.c
index 1ac64450d..4cd746b8b 100644
--- a/drivers/pci/dwc/pcie-tegra.c
+++ b/drivers/pci/dwc/pcie-tegra.c
@@ -58,8 +58,6 @@
 #define APPL_PINMUX_CLKREQ_OVERRIDE            BIT(3)
 #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN  BIT(4)
 #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE     BIT(5)
-#define APPL_PINMUX_CLKREQ_OUT_OVRD_EN         BIT(9)
-#define APPL_PINMUX_CLKREQ_OUT_OVRD            BIT(10)
 #define APPL_PINMUX_PEX_RST_IN_OVERRIDE_EN     BIT(11)

 #define APPL_CTRL                              (0X4)
@@ -4537,8 +4535,8 @@ static int tegra_pcie_dw_runtime_resume(struct device *dev)

        if (pcie->disable_clock_request) {
                val = readl(pcie->appl_base + APPL_PINMUX);
-               val |= APPL_PINMUX_CLKREQ_OUT_OVRD_EN;
-               val |= APPL_PINMUX_CLKREQ_OUT_OVRD;
+               val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN;
+               val &= ~APPL_PINMUX_CLKREQ_OVERRIDE;
                writel(val, pcie->appl_base + APPL_PINMUX);
        }

@@ -4722,8 +4720,8 @@ static int tegra_pcie_dw_resume_noirq(struct device *dev)

        if (pcie->disable_clock_request) {
                val = readl(pcie->appl_base + APPL_PINMUX);
-               val |= APPL_PINMUX_CLKREQ_OUT_OVRD_EN;
-               val |= APPL_PINMUX_CLKREQ_OUT_OVRD;
+               val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN;
+               val &= ~APPL_PINMUX_CLKREQ_OVERRIDE;
                writel(val, pcie->appl_base + APPL_PINMUX);
        }

Will do. Might be end of the week before I get a chance to do this.

Actually, can you point me in the right direction to find that file? I assume its in the kernel sources somewhere?

Yes. I should be in the kernel sources. In case you find some of the kernel sources in ‘nvidia’ or ‘linux-nvidia’, then look for this file out there.

Hi natekinight,

All the public sources are on the dlc.