A question on ptx instructions and SM units

Hi, I am having a question on where the ptx instructions are performed on the SM. For example, Control Flow Instructions, and Comparison and Selection Instructions, etc., (while flops may be obvious).

If you look at this whitepaper:


Figure 6 and 7 are pretty interesting, although it is not clear from them, or the text, where flow control instructions are handled. Figure 7 indicates that logical comparison instructions happen in the CUDA cores.