About PCIe Lane

Hello, I want to compare and confirm Jetson_TX2_NX_Interface_Comparison_Migration_AN_DA-10170-001_v1.0.pdf with Jetson_TX2_NX_Product_Design_Guide_DG-10141-001_v1.1.pdf.

Q1.Regarding “PCIe # 0, Lane 1” and “PCIe # 0, Lane 0” of “Tegra X2 Lanes”, the contents of “Tegra X2 Lanes” in the two tables are different. Which is the correct information?

Q2.Is “na” correct for “PCIe 2, Lane 0” in the “Jetson TX2NX Function Names” row of Table 5?

Q3.Is “PCIe #0, Lane 2” correct for “PCIe 0, Lane 2” in the “Module Pin Names” row of Table 5?

Best regards.

Hi, we are checking this, will update once available.

Hi, the DG is correct, the Jetson TX2 NX table (Table 5) in the Migration AN is not correct. For questions #2/#3, the table really shouldn’t show the Tegra X2 lanes 3:2 since those lanes are not used on the module. These will be corrected in new release. Thanks.

Thank you for reply.
For question 2 and 3,Does it mean that Tegra X2 Lane 3 in table5 is invalid? Where does Tegra X2 lanes 3: 2 represent in table5?

Please take DG as correct reference only.

Thank you for reply.

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