About RTS5420-GR in P3768_A04_Concept_Schematic

Dear

Pin 41 of RTS5420 is 5v input for internal 3.3V LDO in the specsheet.
But VDD_3V3_SYS is connected to Pin 41 on RTS5420 in the P3768_A04 reference shematic.
Could you expalin why VDD_3V3_SYS is connected to Pin41?

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It is just a backup design as internal LDO is not used.

Dear Trumany

Could you expalin why VDD_3V3_SYS is connected to Pin41 instead of 5V?

As said, it is a backup design to give a fix level on the pin but not to enable LDO.

I am also wondering about the same thing. In addition, I would like to know if the 5V input of pins 83 and 84 is not needed if the internal LDO is not used.

Do you mean pin 83 & 87? That’s SNN which means not used.

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