about some mipi-csi parameters

Can anyone check some parameters for me? thanks.

The csi2 lane speed is 350Mbps/lane, HS byte clock is 43.75Mhz . the camera's output is 1280*800@48 .

so at the dts file:

       mclk_khz = "43750";               //    43.75Mhz
       mclk_multiplier = "2.05";         //    49183745/24000000 = 2.049
       pix_clk_hz = "49183745";          //    1280*800*48.031 = 49183745

The mclk_khz is a static parameter ? It will always be "24000" ? After read some of camera's dts file ,I found that the mclk_khz always be "24000".

mclk_khz is sensor input clock. It depend on sensor usually most of sensor is working for 24Mhz.

* A modeX node is required to support v4l2 driver
			* implementation with NVIDIA camera software stack
			* mclk_khz = "";
			* Standard MIPI driving clock, typically 24MHz

so,the mclk_khz is the input frequency of sensor,NOT the output of sensor’s mipi-csi frequency.

and,at the drivers/media/i2c/imx185.c,line 62,there is a macro: IMX185_DEFAULT_CLK_FREQ. The mclk_khz just equals the IMX185_DEFAULT_CLK_FREQ ?

They should are the same value for the same sensor.

Thanks,now I can get the size of 1280*800 pictures(raw8).

at “sensor driver programming guide”,I know that:

Specifies the multiplier to MCLK for timing the capture sequence of the hardware. Use the following equation to calculate this value:
mclk_multiplier = desired ISP clock frequency / mclk.
This value must be larger than pixel_clk_hz / mclk to prevent ISP underrun.

As we know, mclk is 24Mhz .So if I want to let the HS byte clock which at tx2’s csi to be 43.75Mhz,I just set mclk_multiplier to “1.823” ??? 43.75/24=1.82291666 .

What is HS byte clock?

HS byte clock is just another form of lane speed(high speed mode).

The unit of lane speed is bit per second,and the unit of HS byte clock is byte per second.

lane of speed = HS byte clock * 8

If the lane speed is 350Mbps/lane,and the HS byte clock will be 350/8=43.75Mhz.

Pixel of our ar0134 is 60Mhz,the output is parallel(raw8),we use tx358748xbg to translate data from parallel to mipi-csi,there have 2 lanes. And the suitable data output frequency of tx358748xbg should be 480Mbps/s( 60Mhz*8) . Each lane speed should be 240Mbps/s( 480/2) . The suitable Hs byte clock of tx358748xbg is 30Mhz (240/8) .

Now I try to use 350Mbps/s.

The “desired ISP clock frequency” usually tell the pixel clock.

My DTS is:

ar0134_a@10 {
                                    /* Define any required hw resources needed by driver */
                                    /* ie. clocks, io pins, power sources */
                                    /* mclk-index indicates the index of the */
                                    /* mclk-name with in the clock-names array */

                                    clocks = <&tegra_car TEGRA186_CLK_EXTPERIPH1>,
                                             <&tegra_car TEGRA186_CLK_PLLP_OUT0>;
                                    clock-names = "extperiph1", "pllp_grtba";
                                    mclk = "extperiph1";
                                    clock-frequency = <24000000>;

so,the mclk will be 240000000 ???

Yes, here tell the source of the mclk is extperiph1 and rate is 24000000