No progress has been made since the last advice.
The following is a summary of our situation.
To define the sensor (FPGA) that connects to CSI as dev / video0
The driver diverted ov5693 and took the same measures as in the forum below.
A sensor (FPGA) was connected using TX1 and TX2 respectively.
Sensor (FPGA) CSI clock frequency is 300MHz
Why you think 300MHz is right
The CSI Line Rate is set to 620Mbps, but the clock is halved to about 300MHz because the data is DDR.
Below are the results of the experiment
Jetson TX1 settings: 1920 x 1200, 60fps, lane 4
Of course, the conditions were set in the DTS file.
As a result of operation, the frame rate became 60 fps. The acquired data is normal.
Then the same experiment with TX1 replaced by TX2
Jetson TX2 settings: 1920 x 1200, 60fps, lane 4
The conditions were set in the DTS file with reference to TX1.
The TX1 and TX2 DTS files have the following differences.
・ In TX1, the I2C settings of the DTS file have not been changed.
・ In TX2, the lane and port settings were changed in the DTS file.
As a result of operation, the frame rate became 30 fps.
And it seems that the acquired data is missing data on a regular basis.
Different, different perspective experiments
We confirmed the operation with the same TX2 and a sensor (FPGA) with the CSI clock frequency changed to 150MHz.
With that setting, the frame rate was halved to 15fps.
As reported in other posts, TX2 has an SOF acquisition cycle of about 33 msec.
Originally, the cycle should be 16msec.
We think that correct capture is possible if the following notification arrives at 16msec intervals.
- ATOMP_FS
- CHANSEL_PXL_SOF
- CHANSEL_LOAD_FRAMED
Four. CHANSEL_PXL_EOF
Five. ATOMP_FE
The DTS file settings may be insufficient.
If anyone can review it, I would like to publish the DTS file.
Also, please suggest another survey item. We will publish the necessary information.