From the DG-090693-001_v1.3.pdf, When mention PCIE0 clock, it states PEX_CLK5 first, then PEX_CLK3 latter, is it a typo? What’s the difference between the two clock, I mean PEX_CLKx and NVHS0_REFCLK? And CAN0_EN is just a GPIO on the module controlled by the code, but not routed out of the module, right? ‘Cause I can’t find it on the devkit/module pinout.
Thanks.
Yes, it is a typo that PEX_CLK3 should be PEX_CLK5 in table 6-11. PEX_CLKx is for root and NVHS0_REFCLK is for endpoint. CAN0_EN is a GPIO on the module and not routed out of module.
@Trumany , what about PCIE1? And do I need termination resistor out of the module? Where can I get the electrical parameter about these clock?
Thanks.
As note says: The PCIe REFCLK inputs and PCIEx_CLK clock outputs comply to the PCIe CEM specification “REFCLK DC Specifications and AC Timing Requirements.” The clocks are HCSL compatible
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