About using spi on Jetson NANO

Hello,

I have de-compiled kernel_tegra210-p3448-0002-p3449-0000-b00.dtb

manager@manager-desktop:/boot$ ll kernel_tegra210-p3448-0002-p3449-0000-b00.dtb
-rw-r–r-- 1 root root 237201 4월 8 19:01 kernel_tegra210-p3448-0002-p3449-0000-b00.dtb

It says

                    spi1_mosi_pc0 {
                            nvidia,pins = "spi1_mosi_pc0";
                            nvidia,function = "spi1";
                            nvidia,pull = <0x1>;
                            nvidia,tristate = <0x0>;
                            nvidia,enable-input = <0x1>;
                    };

sudo cat /sys/kernel/debug/tegra_pinctrl_reg | grep -i spi

manager@manager-desktop:/boot$ sudo cat /sys/kernel/debug/tegra_pinctrl_reg | grep -i spi
**Bank: 1 Reg: 0x70003050 Val: 0x0000e044 -> spi1_mosi_pc0**
Bank: 1 Reg: 0x70003054 Val: 0x0000e045 -> spi1_miso_pc1
Bank: 1 Reg: 0x70003058 Val: 0x0000e045 -> spi1_sck_pc2
Bank: 1 Reg: 0x7000305c Val: 0x0000e049 -> spi1_cs0_pc3
Bank: 1 Reg: 0x70003060 Val: 0x0000e049 -> spi1_cs1_pc4
Bank: 1 Reg: 0x70003064 Val: 0x00006046 -> spi2_mosi_pb4
Bank: 1 Reg: 0x70003068 Val: 0x00006046 -> spi2_miso_pb5
Bank: 1 Reg: 0x7000306c Val: 0x00006046 -> spi2_sck_pb6
Bank: 1 Reg: 0x70003070 Val: 0x00006046 -> spi2_cs0_pb7
Bank: 1 Reg: 0x70003074 Val: 0x00006045 -> spi2_cs1_pdd0
Bank: 1 Reg: 0x70003078 Val: 0x0000e015 -> spi4_mosi_pc7
Bank: 1 Reg: 0x7000307c Val: 0x0000e015 -> spi4_miso_pd0
Bank: 1 Reg: 0x70003080 Val: 0x0000e015 -> spi4_sck_pc5
Bank: 1 Reg: 0x70003084 Val: 0x0000e015 -> spi4_cs0_pc6
Bank: 1 Reg: 0x70003088 Val: 0x00002015 -> qspi_sck_pee0
Bank: 1 Reg: 0x7000308c Val: 0x00002015 -> qspi_cs_n_pee1
Bank: 1 Reg: 0x70003090 Val: 0x00002015 -> qspi_io0_pee2
Bank: 1 Reg: 0x70003094 Val: 0x00002015 -> qspi_io1_pee3
Bank: 1 Reg: 0x70003098 Val: 0x00002015 -> qspi_io2_pee4
Bank: 1 Reg: 0x7000309c Val: 0x00002015 -> qspi_io3_pee5
Bank: 0 Reg: 0x70000b70 Val: 0x00000001 -> drive_qspi_comp_control
Bank: 0 Reg: 0x70000b78 Val: 0x00000001 -> drive_qspi_lpbk_control
Bank: 0 Reg: 0x70000a78 Val: 0x00808000 -> drive_qspi_comp

Is it right?

Thank you.

Not just modify spi1_mosi_pc0 all of spi1__ need to modify.

1 Like

Hello,

The modification seems to be applied to the dtb with the kernel_ prefix as follows, is that correct? I think you said before that dtb with kernel_ prefix is not created. Could you please check it internally?
kernel_tegra210-p3448-0002-p3449-0000-b00.dtb

Thank you.

Hello,

sudo cat /sys/kernel/debug/tegra_pinctrl_reg | grep -i spi

manager@manager-desktop:~$ !1
sudo cat /sys/kernel/debug/tegra_pinctrl_reg | grep -i spi
[sudo] password for manager: 
Bank: 1 Reg: 0x70003050 Val: 0x0000e044 -> spi1_mosi_pc0
Bank: 1 Reg: 0x70003054 Val: 0x0000e044 -> spi1_miso_pc1
Bank: 1 Reg: 0x70003058 Val: 0x0000e044 -> spi1_sck_pc2
Bank: 1 Reg: 0x7000305c Val: 0x0000e048 -> spi1_cs0_pc3
Bank: 1 Reg: 0x70003060 Val: 0x0000e048 -> spi1_cs1_pc4
Bank: 1 Reg: 0x70003064 Val: 0x00006046 -> spi2_mosi_pb4
Bank: 1 Reg: 0x70003068 Val: 0x00006046 -> spi2_miso_pb5
Bank: 1 Reg: 0x7000306c Val: 0x00006046 -> spi2_sck_pb6
Bank: 1 Reg: 0x70003070 Val: 0x00006046 -> spi2_cs0_pb7
Bank: 1 Reg: 0x70003074 Val: 0x00006045 -> spi2_cs1_pdd0
Bank: 1 Reg: 0x70003078 Val: 0x0000e015 -> spi4_mosi_pc7
Bank: 1 Reg: 0x7000307c Val: 0x0000e015 -> spi4_miso_pd0
Bank: 1 Reg: 0x70003080 Val: 0x0000e015 -> spi4_sck_pc5
Bank: 1 Reg: 0x70003084 Val: 0x0000e015 -> spi4_cs0_pc6
Bank: 1 Reg: 0x70003088 Val: 0x00002015 -> qspi_sck_pee0
Bank: 1 Reg: 0x7000308c Val: 0x00002015 -> qspi_cs_n_pee1
Bank: 1 Reg: 0x70003090 Val: 0x00002015 -> qspi_io0_pee2
Bank: 1 Reg: 0x70003094 Val: 0x00002015 -> qspi_io1_pee3
Bank: 1 Reg: 0x70003098 Val: 0x00002015 -> qspi_io2_pee4
Bank: 1 Reg: 0x7000309c Val: 0x00002015 -> qspi_io3_pee5
Bank: 0 Reg: 0x70000b70 Val: 0x00000001 -> drive_qspi_comp_control
Bank: 0 Reg: 0x70000b78 Val: 0x00000001 -> drive_qspi_lpbk_control
Bank: 0 Reg: 0x70000a78 Val: 0x00808000 -> drive_qspi_comp

The result of applying dtb is as follows.
Is that right?
If this is correct, the signal cannot be checked through the oscilloscope even in this state.
What more can we do?

Thank you.

The REG dump are correct suppose the pin configure should be OK.
Just try if able pass the loopback test.

1 Like

Hello,

I made a loopback test environment in hardware.
SCK and cs signals do not come out.
What can we do?


Thank you.

How about MOSI/MISO?
Does the test show pass?

1 Like

Hello,

I test spi using the spidev_test.c program.
How do I test for MOSI/MISO only?
Can you tell me how?

Thank you.

I mean probe the MOSI/MISO if able see the waveform?
Below link for the loopback test.

https://elinux.org/Jetson/TX1_SPI#Loopback_Testing

1 Like

Hello,

How about this dump?

manager@manager-desktop:~/yhlee/coding$ sudo cat /sys/kernel/debug/tegra_pinctrl_reg | grep -i spi
[sudo] password for manager: 
Bank: 1 Reg: 0x70003050 Val: 0x0000e044 -> spi1_mosi_pc0
Bank: 1 Reg: 0x70003054 Val: 0x0000e044 -> spi1_miso_pc1
Bank: 1 Reg: 0x70003058 Val: 0x0000e044 -> spi1_sck_pc2
Bank: 1 Reg: 0x7000305c Val: 0x0000e048 -> spi1_cs0_pc3
Bank: 1 Reg: 0x70003060 Val: 0x0000e048 -> spi1_cs1_pc4
Bank: 1 Reg: 0x70003064 Val: 0x00006044 -> spi2_mosi_pb4
Bank: 1 Reg: 0x70003068 Val: 0x00006044 -> spi2_miso_pb5
Bank: 1 Reg: 0x7000306c Val: 0x00006044 -> spi2_sck_pb6
Bank: 1 Reg: 0x70003070 Val: 0x00006044 -> spi2_cs0_pb7
Bank: 1 Reg: 0x70003074 Val: 0x00006044 -> spi2_cs1_pdd0
Bank: 1 Reg: 0x70003078 Val: 0x0000e015 -> spi4_mosi_pc7
Bank: 1 Reg: 0x7000307c Val: 0x0000e015 -> spi4_miso_pd0
Bank: 1 Reg: 0x70003080 Val: 0x0000e015 -> spi4_sck_pc5
Bank: 1 Reg: 0x70003084 Val: 0x0000e015 -> spi4_cs0_pc6
Bank: 1 Reg: 0x70003088 Val: 0x00002015 -> qspi_sck_pee0
Bank: 1 Reg: 0x7000308c Val: 0x00002015 -> qspi_cs_n_pee1
Bank: 1 Reg: 0x70003090 Val: 0x00002015 -> qspi_io0_pee2
Bank: 1 Reg: 0x70003094 Val: 0x00002015 -> qspi_io1_pee3
Bank: 1 Reg: 0x70003098 Val: 0x00002015 -> qspi_io2_pee4
Bank: 1 Reg: 0x7000309c Val: 0x00002015 -> qspi_io3_pee5
Bank: 0 Reg: 0x70000b70 Val: 0x00000001 -> drive_qspi_comp_control
Bank: 0 Reg: 0x70000b78 Val: 0x00000001 -> drive_qspi_lpbk_control
Bank: 0 Reg: 0x70000a78 Val: 0x00808000 -> drive_qspi_comp

Thank you.

The REG dump are correct.

1 Like

Hello,

When the jetson nano emmc module is mounted on the devkit carrier board, the signal cannot be observed through the oscilloscope.

What more can I do?

Thank you.

Hello,

  1. devkit carrier board + jetson nano devkit module (spi2)

  2. devkit carrier board + jetson nano emmc module (above REG dump setting)
    No signal.

How can I check the signal in emmc?

Thank you.

Does the spidev_test pass the test?

1 Like

Hello,

In the case of emmc module, only reg dump is normal.

no signal
When I run spidev_test, nothing happens.

What else can we do?

Thank you.

What is spidev_test show?

./spidev_test -D /dev/spidev0.0 -g 16 -s 11000000 -zzz
using device: /dev/spidev0.0
setting spi mode for read,write
setting spi bpw
setting max speed for rd/wr
spi mode: 0
bits per word: 8 bytes per word: 1
max speed: 11000000 Hz (11000 KHz)
no. runs: 1
Using seed:0x62564ff9
loop count = 0
using sequential pattern ....
transfer bytes [16]
0000: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
transfer: Return actual transfer length: 16
receive bytes [16]
0000: 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
transfer: received packet size:16 len:16 stat:0
/dev/spidev0.0: TEST PASSED
====== Transfer stats ====
Transmit:
       total: 16B (0KiB 0MiB)
       total: 1P
       ioerr: 0B (0KiB 0MiB)
       ioerr: 0P
 Rate:
  wire total: -1B/s (0KB/s)
       total: -1B/s (0KB/s)
  wire total: -1P/s
       total: -1P/s
Receive:
       total: 16B (0KiB 0MiB)
       total: 1P
        good: 16B (0KiB 0MiB)
        good: 1P
       ioerr: 0P
     dataerr: 0P
 Rate:
        good: -1B/s (0KB/s)
        good: -1P/s
 packet drop: -1/10000

  Total time: 0.000397s

1 Like

Hello,

manager@manager-desktop:~/yhlee/coding$ ./spidev_test -D /dev/spidev0.0 -g 16 -s 11000000 -zzz
./spidev_test: invalid option – ‘g’
Usage: ./spidev_test [-DsbdlHOLC3]
-D --device device to use (default /dev/spidev1.1)
-s --speed max speed (Hz)
-d --delay delay (usec)
-b --bpw bits per word
-l --loop loopback
-H --cpha clock phase
-O --cpol clock polarity
-L --lsb least significant bit first
-C --cs-high chip select active high
-3 --3wire SI/SO signals shared

It’s something wrong with my spidev_test binary.

Can you tell me how to build spidev_test ?

Thank you.

You can download the binary file from below link.
Rename it as spidev_test and chmod +x for it.

1 Like

Hello,

Thank you.

Hello, @ShaneCCC

Even if the jetson nano emmc module configured as above is connected to the jetson nano devkit carrier board, the signal cannot be checked through the oscilloscope.
I was able to check the signal through the oscilloscope on the jetson nano devkit board that modified the device tree using jetson io.

What should I check to check the signal output even when using the emmc module?



Thank you.