Access SPI controller failed via BPMP IPC in ATF-bl31/trusty

Autonomous Machines Jetson & Embedded Systems Jetson AGX Xavier
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For some reason, I need to enable SPI controller driver in ATF-bl31(Arm-trusted-firmware) or Trusty on Jetson AGX Xavier. I am using public Jetson R32.2.3 release code(ATF/Trusty/Cboot).

Since the BPMP driver(in ATF) only supports SE, I ported the BPMP-FW interface code from Cboot to ATF.

I wrote a simple code to init. the IPC and configured the clock settings for SPI1, it works in Cboot (accesses SPI1 OK) . But when ATF-bl31 accesses the SPI1 I/O range (0x03210000~), it hangs.

The procedures including: 1. tegrabl_ipc_init(), 2. tegrabl_car_rst_set(), 3. tegrabl_car_clk_enable() , 4. tegrabl_car_set_clk_src(), 5. tegrabl_car_set_clk_rate(), 6. tegrabl_car_rst_clear().

The major difference are BPMP_IPC_TX(RX)_PHY_BASE(0x4004C000/0x4004D000 in ATF/Trusty, 0x4004E000/0x4004F000 in Cboot)

Could Nvidia Engineer tell me what else needs to be done before accessing the SPI controller in ATF-bl31/Trusty? Thank you.

3

May need time to consult with developer first.

1 Like
4

The SPI1 register aperture should then be added to platform memory map (plat_setup.c).

1 Like
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Thanks for your reply.

However, my previous test has already added it to memory map(plat_setup.c), otherwise accessing SPI1 will generate a sync error or data abort.

8

Hello ycllin,
I have tried to bring up pcie via BPMP in ATF bl31. It works in Cboot but
hangs in atf bl31. I also found the BPMP base address is different with Cboot’s. Do you solve your problem?

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Atf runs in EL3 and Cboot in EL2.
I think base addresses are different becuase Atf has secure BPMP channel and Cboot has NS channel.