Accessing DRAM Mode registers On Jetson AGX Orin


I am trying to have the memory controller run mode register read commands to the external LPDDR5 memory for a Jetson AGX Orin board I am using.

The Linux driver for an earlier Tegra version shows some of these registers being directly read:

emc_read_lpddr_mode_register(emc, emem_dev, 5, &emc->manufacturer_id);
emc_read_lpddr_mode_register(emc, emem_dev, 6, &emc->revision_id1);
emc_read_lpddr_mode_register(emc, emem_dev, 7, &emc->revision_id2);
emc_read_lpddr_mode_register(emc, emem_dev, 8, &emc->basic_conf4.value);

However, more recent tegra driver doesn’t show similar “emc” bindings:

Question 1:

Does the Jetson AGX Orin board include an external memory controller similar to previous Nvidia products?

Question 1a: If the answer to Q1 is no, what controller plays the role of running mode register read commands to the DRAM external memory device?

Question 2: What documentation describes the software APIs to this emc?

Given that SoC development boards often offer this capability, I have also downloaded several board support package software tools for this board, and have looked for tools to run mode register read commands at boot time, but did not find any.

Question 3: Do any tools supported by Nvidia allow running DRAM mode register read commands at boot time?

Thank you in advance

Please share more detail about the use-case. We would like to have a more secure software so this execution may be prohibited.

Hi Dane

The use case is for software to access in read-only mode the memory’s Jedec standard mode registers, which includes benign information such as the manufacturer ID, revision ID.

Other vendors offer detailed methods to do so, for example:

Please let me know if you need more details about this use case


So you need the information about manufacturer and revision of the DRAM? We would like to confirm what information is required and see if there is other methods of fetching the information.

Hi Dane

We would like to be able to read out the LPDDR5 interface configuration parameter such as for example clock mode, write latency, IO width, latency mode, read latency, pull down drive, bank organization.

I mentioned the manufacturer ID as an example because an early version of the Nvidia driver supports reading it, as I cited in my first question on this ticket.



Please check the node /sys/kernel/debug/bpmp/debug/emc as root. This is the only DRAM info that get revealed here.

Hi Wayne

Thanks for your answer.

There is apparently one direct interface to DRAM mode registers in this folder: “dram_info”, which prints the content of MR5-MR8.

Q1: is there another portion of this folder that allows access to DRAM mode registers?
Q2: is there documentation describing how the tables found in this folder operate in the controller?
Q3: is the source code for the “dram_info” interface and any other driver accessing DRAM mode registers open or closed to developers?


For now we don’t have further access to the information. For security concern some operation is prohibited.

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