Accessing Registers

Hi,
per https://forums.developer.nvidia.com/t/how-to-adjustment-mipi-dsi-signal-driven-strength-for-tx2/54646 I have tried to read registers from the DSI_PADCTL registers (per chapter 24 in TRM).

I’ve noticed that there is incorrect correlation between Registers’ offset and their byte offset to the one dictated by the following function:
GET_BYTE_OFFSET(reg) ((reg > 8) ? ((reg + 1) * 4) : (reg * 4))
If I work with TX2 which one is the correct the one in the TRM or the above?

devmem2 provides the option to access b(1 byte), h(2bytes), w(4 bytes) to/from the mapped memory. When I try to the following applying an offset that is not divisble by 8 I get a failure:
devmem2 0x15880034 w - failure
while
devmem2 0x15880034 h - OK but only (16 bits)

devmem2 0x15880030 w - OK
while
devmem2 0x15880030 h - OK but only (16 bits).

What is the correct way to access these registers?

BTW, I read also “NVIDIA JETSON TX1 MIPI DSI/CSI DESIGN AND TUNING” found nothing there.

Regards.

Hi,

Please also try devmem tool from busybox.

WayneWWW, hi,

as always thanks for the support, it works with devmem.

for other users:
install busybox:
sudo apt-get install busybox
sudo /bin/busybox devmem - help
sudo /bin/busybox devmem 0x15880000 32 - read 32 bits
sudo /bin/busybox devmem 0x15880004 32 - read 32 bits
sudo /bin/busybox devmem 0x15880000 32 0x0 - write 32 bits

Though I am still puzled by the offsets. could you please reply to the offsets written in the TRM and the GET_BYTE_OFFSET.
Per the TRM:
register (offset) 8 is at address 0x15880020 (0x15880000 + 0x20 Byte Offset)
register (offset) 9 is at address 0x15880024 (0x15880000 + 0x24 Byte Offset)

while per GET_BYTE_OFFSET:
register (offset) 8 is at address 0x15880020 (0x15880000 + 0x20 Byte Offset)
register (offset) 9 is at address 0x15880028 (0x15880000 + 0x28 Byte Offset)

could you please resolve this contradiction?

Regards.

Hi,

can anyone from NVidia reply on above contradiction?

Regards.

Hi igal.kroyter,

Sorry for late reply.
I just get some time to recap what is going on in the driver code. Your question has been asked by other user last year.

I believe this one can reply your question. Because TX2 and TX1 share the same driver code, the code has only one header file to handle the difference after offset 0x8. Your result based on TRM is correct. The problem is this offset calculation formula in dsi.c driver code is not for TX2, but for TX1. Thus, it is wrong for you to directly put the offset from TX2 TRM to driver code formula.

Wayne, hi, thanks.

So the fact that we see no affect in the DSI (A) signals’ (lane0, lane1, clk) pattern although we change the pull-ups, pull-downs or even the slew rate might be due to?

Hi,

can anyone from NVidia reply on above contradiction?

Regards.

Hi,

can anyone from NVidia reply on above contradiction?

Regards.

Hello,

As I explained, there is no contradiction. Please don’t treat every problem as the same one.
If you have other problem in DSI, please open a topic and tell us your current setup and dts change.