per https://forums.developer.nvidia.com/t/how-to-adjustment-mipi-dsi-signal-driven-strength-for-tx2/54646 I have tried to read registers from the DSI_PADCTL registers (per chapter 24 in TRM).
I’ve noticed that there is incorrect correlation between Registers’ offset and their byte offset to the one dictated by the following function:
GET_BYTE_OFFSET(reg) ((reg > 8) ? ((reg + 1) * 4) : (reg * 4))
If I work with TX2 which one is the correct the one in the TRM or the above?
devmem2 provides the option to access b(1 byte), h(2bytes), w(4 bytes) to/from the mapped memory. When I try to the following applying an offset that is not divisble by 8 I get a failure:
devmem2 0x15880034 w - failure
devmem2 0x15880034 h - OK but only (16 bits)
devmem2 0x15880030 w - OK
devmem2 0x15880030 h - OK but only (16 bits).
What is the correct way to access these registers?
BTW, I read also “NVIDIA JETSON TX1 MIPI DSI/CSI DESIGN AND TUNING” found nothing there.