I did some more digging, and I believe that the SPI clock is being shut off after the initial transfer.
I was looking through the Tegra X2 technical reference manual in order to enable the clocks from the registers, and I found the following section (page 3973):
The CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0, CLK_RST_CONTROLLER_CLK_OUT_ENB_V_0, and
CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0 registers in the CAR (Clock and Reset) block contain the enable bits for the
SPI controller. In addition, the clock source and divider registers (CLK_SOURCE_SBC1, CLK_SOURCE_SBC2,
CLK_SOURCE_SBC3, CLK_SOURCE_SBC4, CLK_SOURCE_SBC5, and CLK_SOURCE_SBC6) contain the 2-bit field
SBCx_CLK_SRC to determine the PLL clock source, while the SBCx_CLK_DIVISOR field determines the divide ratio.
It seems as if these register names are taken from the Tegra X1 manual, which has these registers, but they are not present in the TX2 manual. Can you tell me which clock registers need to be activated for the TX2?
I believe one would be CLK_RST_CONTROLLER_CLK_OUT_ENB__0 at 0x05231000, but this seems to not like being written (despite th PLL register seemingly enabled).