Accessing SPI Memory Registers

Robotics & Edge Computing Jetson & Embedded Systems Jetson TX2
1

Does anyone have any insight on accessing the SPI memory registers?

I have had no problems reading and writing the GPIO registers, but I cannot do anything with the addresses for SPI. Specifically, I am interested in SPI1, which begins at 0x03210000.

I have tried with and without SPI enabled in the kernel configuration, and either way, attempting to access these registers results in a system freezeup (in Linux or in Erika3 on the Jailhouse hypervisor) with no error messages.

This is necessary as I am writing an SPI driver for the Erika3 RTOS.

2

You may need to enable some clock and power. Please try to access this reg from spi dirver spi-tegra114.c.

3

Hi Shane,

Thanks for the response. I believe that the port is receiving power and clock, as I have tried with the spi-tegra114.c driver enabled. I have also tried with spidev active on the device, and I get the same result.

Clearly the register can be accessed, as spidev runs successfully, but I am not sure how I can get access to it.

Any thoughts?

4

The debug fs is a way. You can implement a debug fs in the spi driver to access the REG from the user space.

5

Hi Shane,

I did some more digging, and I believe that the SPI clock is being shut off after the initial transfer.

I was looking through the Tegra X2 technical reference manual in order to enable the clocks from the registers, and I found the following section (page 3973):

The CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0, CLK_RST_CONTROLLER_CLK_OUT_ENB_V_0, and
CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0 registers in the CAR (Clock and Reset) block contain the enable bits for the
SPI controller. In addition, the clock source and divider registers (CLK_SOURCE_SBC1, CLK_SOURCE_SBC2,
CLK_SOURCE_SBC3, CLK_SOURCE_SBC4, CLK_SOURCE_SBC5, and CLK_SOURCE_SBC6) contain the 2-bit field
SBCx_CLK_SRC to determine the PLL clock source, while the SBCx_CLK_DIVISOR field determines the divide ratio.

It seems as if these register names are taken from the Tegra X1 manual, which has these registers, but they are not present in the TX2 manual. Can you tell me which clock registers need to be activated for the TX2?

I believe one would be CLK_RST_CONTROLLER_CLK_OUT_ENB__0 at 0x05231000, but this seems to not like being written (despite th PLL register seemingly enabled).

6

Try to use the debugfs to enable it from

echo 1 > /sys/kernel/debug/bpmp/debug/clk/spi*/state
7

This works! I now have access to the SPI registers. Thank you so much!