Hi,Sharad.
Codec did not probe successfully. I added “printk()” to the “aic32x4_codec_probe()” function; but it was not executed.
tlv320aic32x4.c
static int aic32x4_codec_probe(struct snd_soc_codec *codec)
{
struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
u32 tmp_reg;
printk(KERN_ERR "aic32x4:===========probe===============");
if (gpio_is_valid(aic32x4->rstn_gpio)) {
ndelay(10);
gpio_set_value(aic32x4->rstn_gpio, 1);
}
snd_soc_write(codec, AIC32X4_RESET, 0x01);
/* Power platform configuration */ //modify 2019.8.21
//if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
snd_soc_write(codec, AIC32X4_MICBIAS, AIC32X4_MICBIAS_LDOIN |
AIC32X4_MICBIAS_2075V);
//}
if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
snd_soc_write(codec, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
AIC32X4_LDOCTLEN : 0;
snd_soc_write(codec, AIC32X4_LDOCTL, tmp_reg);
tmp_reg = snd_soc_read(codec, AIC32X4_CMMODE);
if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36)
tmp_reg |= AIC32X4_LDOIN_18_36;
if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED)
tmp_reg |= AIC32X4_LDOIN2HP;
snd_soc_write(codec, AIC32X4_CMMODE, tmp_reg);
/* Mic PGA routing */
if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K)
snd_soc_write(codec, AIC32X4_LMICPGANIN,
AIC32X4_LMICPGANIN_IN2R_10K);
else
snd_soc_write(codec, AIC32X4_LMICPGANIN,
AIC32X4_LMICPGANIN_CM1L_10K);
if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K)
snd_soc_write(codec, AIC32X4_RMICPGANIN,
AIC32X4_RMICPGANIN_IN1L_10K);
else
snd_soc_write(codec, AIC32X4_RMICPGANIN,
AIC32X4_RMICPGANIN_CM1R_10K);
/*
* Workaround: for an unknown reason, the ADC needs to be powered up
* and down for the first capture to work properly. It seems related to
* a HW BUG or some kind of behavior not documented in the datasheet.
*/
tmp_reg = snd_soc_read(codec, AIC32X4_ADCSETUP);
snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg |
AIC32X4_LADC_EN | AIC32X4_RADC_EN);
snd_soc_write(codec, AIC32X4_ADCSETUP, tmp_reg);
#if 1 //add 2019.8.21
snd_soc_write(codec, AIC32X4_CLKMUX, 0x07);
snd_soc_write(codec, AIC32X4_PLLPR, 0x92);
snd_soc_write(codec, AIC32X4_PLLJ, 0x20);
snd_soc_write(codec, AIC32X4_PLLDMSB, 0x00);
snd_soc_write(codec, AIC32X4_PLLDLSB, 0x00);
snd_soc_write(codec, AIC32X4_NADC, 0x84);
snd_soc_write(codec, AIC32X4_MADC, 0x84);
snd_soc_write(codec, AIC32X4_AOSR, 0x80);
snd_soc_write(codec, AIC32X4_DOSRLSB, 0x80);
snd_soc_write(codec, AIC32X4_DOSRMSB, 0x00);
snd_soc_write(codec, AIC32X4_DACSETUP, 0xD4);
snd_soc_write(codec, AIC32X4_LOLROUTE, 0x08);
snd_soc_write(codec, AIC32X4_LORROUTE, 0x08);
snd_soc_write(codec, AIC32X4_LOLGAIN, 0x1D);
snd_soc_write(codec, AIC32X4_LORGAIN, 0x1D);
snd_soc_write(codec, AIC32X4_LDACVOL, 0xB3);
snd_soc_write(codec, AIC32X4_RDACVOL, 0xB3);
snd_soc_write(codec, AIC32X4_LMICPGAPIN, 0x00);
snd_soc_write(codec, AIC32X4_LMICPGANIN, 0x10);
snd_soc_write(codec, AIC32X4_RMICPGAPIN, 0x10);
snd_soc_write(codec, AIC32X4_RMICPGANIN, 0x40);
snd_soc_write(codec, AIC32X4_LMICPGAVOL, 0x5A);
snd_soc_write(codec, AIC32X4_RMICPGAVOL, 0x5A);
snd_soc_write(codec, AIC32X4_ADCSETUP, 0xC0);
snd_soc_write(codec, AIC32X4_ADCFGA, 0x00);
snd_soc_write(codec, AIC32X4_PWRCFG, 0x08);
snd_soc_write(codec, AIC32X4_LDOCTL, 0x01);
snd_soc_write(codec, 0xFB, 0x01);
snd_soc_write(codec, AIC32X4_CMMODE, 0x00);
snd_soc_write(codec, 0x98, 0x28);
snd_soc_write(codec, AIC32X4_OUTPWRCTL, 0x0C);
#endif
return 0;
}
static int aic32x4_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_codec *codec = dai->codec;
struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
u8 data;
int i;
i = aic32x4_get_divs(aic32x4->sysclk, params_rate(params));
if (i < 0) {
printk(KERN_ERR "aic32x4: sampling rate not supported\n");
return i;
}
#if 0 //modify 2019.8.21
/* Use PLL as CODEC_CLKIN and DAC_MOD_CLK as BDIV_CLKIN */
snd_soc_write(codec, AIC32X4_CLKMUX, AIC32X4_PLLCLKIN);
snd_soc_write(codec, AIC32X4_IFACE3, AIC32X4_DACMOD2BCLK);
/* We will fix R value to 1 and will make P & J=K.D as varialble */
data = snd_soc_read(codec, AIC32X4_PLLPR);
data &= ~(7 << 4);
snd_soc_write(codec, AIC32X4_PLLPR,
(data | (aic32x4_divs[i].p_val << 4) | 0x01));
snd_soc_write(codec, AIC32X4_PLLJ, aic32x4_divs[i].pll_j);
snd_soc_write(codec, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8));
snd_soc_write(codec, AIC32X4_PLLDLSB,
(aic32x4_divs[i].pll_d & 0xff));
/* NDAC divider value */
data = snd_soc_read(codec, AIC32X4_NDAC);
data &= ~(0x7f);
snd_soc_write(codec, AIC32X4_NDAC, data | aic32x4_divs[i].ndac);
/* MDAC divider value */
data = snd_soc_read(codec, AIC32X4_MDAC);
data &= ~(0x7f);
snd_soc_write(codec, AIC32X4_MDAC, data | aic32x4_divs[i].mdac);
/* DOSR MSB & LSB values */
snd_soc_write(codec, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8);
snd_soc_write(codec, AIC32X4_DOSRLSB,
(aic32x4_divs[i].dosr & 0xff));
/* NADC divider value */
data = snd_soc_read(codec, AIC32X4_NADC);
data &= ~(0x7f);
snd_soc_write(codec, AIC32X4_NADC, data | aic32x4_divs[i].nadc);
/* MADC divider value */
data = snd_soc_read(codec, AIC32X4_MADC);
data &= ~(0x7f);
snd_soc_write(codec, AIC32X4_MADC, data | aic32x4_divs[i].madc);
/* AOSR value */
snd_soc_write(codec, AIC32X4_AOSR, aic32x4_divs[i].aosr);
/* BCLK N divider */
data = snd_soc_read(codec, AIC32X4_BCLKN);
data &= ~(0x7f);
snd_soc_write(codec, AIC32X4_BCLKN, data | aic32x4_divs[i].blck_N);
data = snd_soc_read(codec, AIC32X4_IFACE1);
data = data & ~(3 << 4);
switch (params_width(params)) {
case 16:
break;
case 20:
data |= (AIC32X4_WORD_LEN_20BITS << AIC32X4_DOSRMSB_SHIFT);
break;
case 24:
data |= (AIC32X4_WORD_LEN_24BITS << AIC32X4_DOSRMSB_SHIFT);
break;
case 32:
data |= (AIC32X4_WORD_LEN_32BITS << AIC32X4_DOSRMSB_SHIFT);
break;
}
snd_soc_write(codec, AIC32X4_IFACE1, data);
#endif
if (params_channels(params) == 1) {
data = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN;
} else {
if (aic32x4->swapdacs)
data = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN;
else
data = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
}
snd_soc_update_bits(codec, AIC32X4_DACSETUP, AIC32X4_DAC_CHAN_MASK,
data);
return 0;
}
I added “CONFIG_SND_SOC_TLV320AIC32X4=y” and “CONFIG_SND_SOC_TLV320AIC32X4_I2C=y” to the tegra_defconfig file.
tegra_defconfig
CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
CONFIG_IRQ_POLL=y
CONFIG_ARCH_TEGRA_18x_SOC=y
CONFIG_ARCH_TEGRA_19x_SOC=y
CONFIG_ARCH_TEGRA_23x_SOC=y
CONFIG_SND_SOC_TLV320AIC32X4=y
CONFIG_SND_SOC_TLV320AIC32X4_I2C=y
Kconfig
config SND_SOC_TEGRA_T186REF_MOBILE_ALT
tristate "SoC Audio support for T186Ref Mobile"
depends on SND_SOC_TEGRA_T186REF_ALT
select SND_SOC_RT5659
select SND_SOC_SGTL5000
select SND_SOC_TLV320AIC32X4
select SND_SOC_TLV320AIC32X4_I2C
help
Say Y or M here.
tegra_asoc_utils_alt.c
int tegra_alt_asoc_utils_set_parent(struct tegra_asoc_audio_clock_info *data,
int is_i2s_master)
{
int ret = -ENODEV;
if (is_i2s_master) {
ret = clk_set_parent(data->clk_cdev1, data->clk_pll_a_out0);
if (ret) {
dev_err(data->dev, "Can't set clk cdev1/extern1 parent");
return ret;
}
} else {
ret = clk_set_parent(data->clk_cdev1, data->clk_m);
if (ret) {
dev_err(data->dev, "Can't set clk cdev1/extern1 parent");
return ret;
}
//ret = clk_set_rate(data->clk_cdev1, 13000000); //modify 2019.8.21
ret = clk_set_rate(data->clk_cdev1, 12000000);
if (ret) {
dev_err(data->dev, "Can't set clk rate");
return ret;
}
}
return 0;
}
tegra_machine_driver_mobile.c
static int tegra_machine_dai_init(struct snd_soc_pcm_runtime *runtime,
int rate,
int channels,
u64 formats,
bool is_playback)
{
struct snd_soc_card *card = runtime->card;
struct tegra_machine *machine = snd_soc_card_get_drvdata(card);
struct snd_soc_pcm_stream *dai_params;
unsigned int clk_out_rate = 0, mclk = 0;
int err, codec_rate, clk_rate;
struct snd_soc_pcm_runtime *rtd;
codec_rate = tegra_machine_srate_values[machine->rate_via_kcontrol];
clk_rate = (machine->rate_via_kcontrol) ? codec_rate : rate;
if (!machine->soc_data->is_clk_rate_via_dt) {
/* TODO remove this hardcoding */
/* aud_mclk, 256 times the sample rate */
clk_out_rate = clk_rate << 8;
switch (clk_rate) {
case 11025:
mclk = 22579200;
break;
case 22050:
case 44100:
case 88200:
case 176400:
mclk = 45158400;
break;
case 8000:
mclk = 24576000;
break;
case 16000:
case 32000:
case 48000:
case 64000:
case 96000:
case 192000:
default:
mclk = 49152000;
break;
}
err = tegra210_xbar_set_clock(mclk);
if (err < 0) {
dev_err(card->dev,
"Can't configure xbar clock = %d Hz\n", mclk);
return err;
}
}
err = tegra_alt_asoc_utils_set_rate(&machine->audio_clock, clk_rate,
mclk, clk_out_rate);
if (err < 0) {
dev_err(card->dev, "Can't configure clocks\n");
return err;
}
if (machine->soc_data->is_clk_rate_via_dt)
clk_out_rate = machine->audio_clock.set_clk_out_rate;
pr_debug("pll_a_out0 = %d Hz, aud_mclk = %d Hz, codec rate = %d Hz\n",
machine->audio_clock.set_mclk,
machine->audio_clock.set_clk_out_rate, clk_rate);
/* TODO: should we pass here clk_rate ? */
err = tegra_machine_set_params(card, machine, rate, channels, formats);
if (err < 0)
return err;
//add 2019.8.21
rtd = snd_soc_get_pcm_runtime(card, "ti-playback-i2s1");
printk(KERN_ERR "tegra_machine_dai_init:====ti-playback-i2s1-rtd =====\n");
if (rtd) {
dai_params =
(struct snd_soc_pcm_stream *)rtd->dai_link->params;
dai_params->rate_min = clk_rate;
dai_params->formats = (machine->fmt_via_kcontrol == 2) ?
(1ULL << SNDRV_PCM_FORMAT_S32_LE) : formats;
if (machine->is_hs_supported) {
err = snd_soc_dai_set_sysclk(rtd->codec_dai,
0, 12000000, SND_SOC_CLOCK_IN);
if (err < 0) {
dev_err(card->dev, "codec_dai clock not set\n");
return err;
}
}
}
rtd = snd_soc_get_pcm_runtime(card, "ti-playback-i2s2");
printk(KERN_ERR "tegra_machine_dai_init:====ti-playback-i2s2-rtd =====\n");
if (rtd) {
dai_params =
(struct snd_soc_pcm_stream *)rtd->dai_link->params;
dai_params->rate_min = clk_rate;
dai_params->formats = (machine->fmt_via_kcontrol == 2) ?
(1ULL << SNDRV_PCM_FORMAT_S32_LE) : formats;
if (machine->is_hs_supported) {
err = snd_soc_dai_set_sysclk(rtd->codec_dai,
0, 12000000, SND_SOC_CLOCK_IN);
if (err < 0) {
dev_err(card->dev, "codec_dai clock not set\n");
return err;
}
}
}
return 0;
}
static void dai_link_setup(struct platform_device *pdev)
{
struct snd_soc_card *card = platform_get_drvdata(pdev);
struct tegra_machine *machine = snd_soc_card_get_drvdata(card);
struct snd_soc_codec_conf *tegra_machine_codec_conf = NULL;
struct snd_soc_codec_conf *tegra_new_codec_conf = NULL;
struct snd_soc_dai_link *tegra_machine_dai_links = NULL;
struct snd_soc_dai_link *tegra_machine_codec_links = NULL;
const char *codec_dai_name;
int i;
/* set new codec links and conf */
tegra_machine_codec_links = tegra_machine_new_codec_links(pdev,
tegra_machine_codec_links,
&machine->num_codec_links);
if (!tegra_machine_codec_links)
goto err_alloc_dai_link;
/* set codec init */
//modify 2019.8.21
for (i = 0; i < machine->num_codec_links; i++) {
if (tegra_machine_codec_links[i].name) {
if (strstr(tegra_machine_codec_links[i].name,
"ti-playback-i2s1") ||
strstr(tegra_machine_codec_links[i].name,
"ti-playback-i2s2")) {
codec_dai_name =
tegra_machine_codec_links[i].codec_dai_name;
if (!strcmp("dit-hifi", codec_dai_name)) {
dev_info(&pdev->dev, "This is a dummy codec\n");
machine->is_hs_supported = false;
} else {
machine->is_hs_supported = true;
tegra_machine_codec_links[i].init =
tegra_machine_rt565x_init;
}
} else if (strstr(tegra_machine_codec_links[i].name,
"dspk-playback-r")) {
tegra_machine_codec_links[i].init =
tegra_machine_dspk_init;
} else if (strstr(tegra_machine_codec_links[i].name,
"dspk-playback-l")) {
tegra_machine_codec_links[i].init =
tegra_machine_dspk_init;
} else if (strstr(tegra_machine_codec_links[i].name,
"fe-pi-audio-z-v2")) {
tegra_machine_codec_links[i].init =
tegra_machine_fepi_init;
}
}
}
tegra_new_codec_conf = tegra_machine_new_codec_conf(pdev,
tegra_new_codec_conf,
&machine->num_codec_links);
if (!tegra_new_codec_conf)
goto err_alloc_dai_link;
/* get the xbar dai link/codec conf structure */
tegra_machine_dai_links = machine->soc_data->get_dai_link();
if (!tegra_machine_dai_links)
goto err_alloc_dai_link;
tegra_machine_codec_conf = machine->soc_data->get_codec_conf();
if (!tegra_machine_codec_conf)
goto err_alloc_dai_link;
/* set ADMAIF dai_ops */
for (i = machine->soc_data->admaif_dai_link_start;
i <= machine->soc_data->admaif_dai_link_end; i++)
tegra_machine_set_dai_ops(i, &tegra_machine_pcm_ops);
/* set sfc dai_init */
tegra_machine_set_dai_init(machine->soc_data->sfc_dai_link,
&tegra_machine_sfc_init);
#if IS_ENABLED(CONFIG_SND_SOC_TEGRA210_ADSP_ALT)
/* set ADSP PCM/COMPR */
for (i = machine->soc_data->adsp_pcm_dai_link_start;
i <= machine->soc_data->adsp_pcm_dai_link_end; i++) {
tegra_machine_set_dai_ops(i, &tegra_machine_pcm_ops);
}
/* set ADSP COMPR */
for (i = machine->soc_data->adsp_compr_dai_link_start;
i <= machine->soc_data->adsp_compr_dai_link_end; i++) {
tegra_machine_set_dai_compr_ops(i,
&tegra_machine_compr_ops);
}
#endif
if (machine->soc_data->is_asrc_available) {
/* set ASRC params. The default is 2 channels */
for (i = 0; i < 6; i++) {
tegra_machine_set_dai_params(TEGRA186_DAI_LINK_ASRC1_TX1
+ i, (struct snd_soc_pcm_stream *)
&tegra_machine_asrc_link_params[i]);
tegra_machine_set_dai_params(TEGRA186_DAI_LINK_ASRC1_RX1
+ i, (struct snd_soc_pcm_stream *)
&tegra_machine_asrc_link_params[i]);
}
}
/* append machine specific dai_links */
card->num_links = machine->soc_data->append_dai_link(
tegra_machine_codec_links, 2 * machine->num_codec_links);
tegra_machine_dai_links = machine->soc_data->get_dai_link();
card->dai_link = tegra_machine_dai_links;
/* append machine specific codec_conf */
card->num_configs = machine->soc_data->append_codec_conf(
tegra_new_codec_conf, machine->num_codec_links);
tegra_machine_codec_conf = machine->soc_data->get_codec_conf();
card->codec_conf = tegra_machine_codec_conf;
return;
err_alloc_dai_link:
tegra_machine_remove_dai_link();
tegra_machine_remove_codec_conf();
}
tegra186-quill-common.dtsi
i2c@3180000 {
status = "okay";
aic32x4_1: tlv320aic32x4.2-0018@18{
compatible = "ti,tlv320aic32x4";
status = "okay";
reg = <0x18>;
clocks = <&tegra_car TEGRA186_CLK_AUD_MCLK>;
clock-names = "mclk";
};
};
i2c@3160000 {
status = "okay";
aic32x4: tlv320aic32x4.0-0018@18{
compatible = "ti,tlv320aic32x4";
status = "okay";
reg = <0x18>;
clocks = <&tegra_car TEGRA186_CLK_AUD_MCLK>;
clock-names = "mclk";
};
};
tegra_sound: sound {
compatible = "nvidia,tegra-audio-t186ref-mobile-rt565x";
//nvidia,model = "tegra-snd-t186ref-mobile-rt565x";
nvidia,model = "tegra-asoc:";
nvidia,num-codec-link = <12>;
nvidia,num-clk = <8>;
nvidia,clk-rates = < 270950400 /* PLLA_x11025_RATE */
11289600 /* AUD_MCLK_x11025_RATE */
45158400 /* PLLA_OUT0_x11025_RATE */
45158400 /* AHUB_x11025_RATE */
245760000 /* PLLA_x8000_RATE */
12288000 /* AUD_MCLK_x8000_RATE */
49152000 /* PLLA_OUT0_x8000_RATE */
49152000 >;/* AHUB_x8000_RATE */
clocks = <&tegra_car TEGRA186_CLK_PLLP_OUT0>,
<&tegra_car TEGRA186_CLK_PLLA>,
<&tegra_car TEGRA186_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA186_CLK_AHUB>,
<&tegra_car TEGRA186_CLK_CLK_M>,
<&tegra_car TEGRA186_CLK_AUD_MCLK>;
clock-names = "pll_p_out1", "pll_a", "pll_a_out0", "ahub",
"clk_m", "extern1";
resets = <&tegra_car TEGRA186_RESET_AUD_MCLK>;
reset-names = "extern1_rst";
status = "okay";
nvidia,audio-routing =
"x IN2_R", "x Mic",
"x IN2_L", "x Mic",
"x Headphone", "x LOR",
"x Headphone", "x LOL",
"y IN2_R", "y Mic",
"y IN2_L", "y Mic",
"y Headphone", "y LOR",
"y Headphone", "y LOL";
/*
"x Headphone", "x OUT",
"x IN", "x Mic",
"y Headphone", "y OUT",
"y IN", "y Mic",
"z Headphone", "z OUT",
"z IN", "z Mic",
"m Headphone", "m OUT",
"m IN", "m Mic",
"n Headphone", "n OUT",
"n IN", "n Mic",
"o Headphone", "o OUT",
"o IN", "o Mic",
"a IN", "a Mic",
"b IN", "b Mic",
"c IN", "c Mic",
"d IN", "d Mic",
"d1 Headphone", "d1 OUT",
"d2 Headphone", "d2 OUT";
*/
nvidia,xbar = <&tegra_axbar>;
rt565x_dai_link: nvidia,dai-link-1 {
link-name = "ti-playback-i2s2";
cpu-dai = <&tegra_i2s2>;
codec-dai = <&aic32x4_1>;
cpu-dai-name = "I2S2";
codec-dai-name = "tlv320aic32x4-hifi";
tx-mask = <0xFF>;
rx-mask = <0xFF>;
format = "i2s";
bitclock-slave;
frame-slave;
bitclock-noninversion;
frame-noninversion;
bit-format = "s16_le";
bclk_ratio = <0>;
srate = <48000>;
num-channel = <1>;
ignore_suspend;
name-prefix = "x";
status = "okay";
};
nvidia,dai-link-2 {
link-name = "ti-playback-i2s1";
cpu-dai = <&tegra_i2s1>;
codec-dai = <&aic32x4>;
cpu-dai-name = "I2S1";
codec-dai-name = "tlv320aic32x4-hifi";
tx-mask = <0xFF>;
rx-mask = <0xFF>;
format = "i2s";
bitclock-slave;
frame-slave;
bitclock-noninversion;
frame-noninversion;
bit-format = "s16_le";
bclk_ratio = <0>;
srate = <48000>;
num-channel = <1>;
ignore_suspend;
name-prefix = "y";
status = "okay";
};
nvidia,dai-link-3 {
link-name = "spdif-dit-2";
cpu-dai = <&tegra_i2s3>;
codec-dai = <&spdif_dit2>;
cpu-dai-name = "I2S3";
codec-dai-name = "dit-hifi";
format = "i2s";
bit-format = "s16_le";
bclk_ratio = <1>;
srate = <48000>;
num-channel = <2>;
ignore_suspend;
name-prefix = "z";
status = "disabled";
};
nvidia,dai-link-4 {
link-name = "spdif-dit-3";
cpu-dai = <&tegra_i2s4>;
codec-dai = <&spdif_dit3>;
cpu-dai-name = "I2S4";
codec-dai-name = "dit-hifi";
format = "i2s";
bit-format = "s16_le";
bclk_ratio = <1>;
srate = <48000>;
num-channel = <2>;
ignore_suspend;
name-prefix = "m";
status = "disabled";
};
nvidia,dai-link-5 {
link-name = "spdif-dit-4";
cpu-dai = <&tegra_i2s5>;
codec-dai = <&spdif_dit4>;
cpu-dai-name = "I2S5";
codec-dai-name = "dit-hifi";
format = "i2s";
bit-format = "s16_le";
bclk_ratio = <1>;
srate = <48000>;
num-channel = <2>;
ignore_suspend;
name-prefix = "n";
status = "disabled";
};
nvidia,dai-link-6 {
link-name = "spdif-dit-6";
cpu-dai = <&tegra_i2s6>;
codec-dai = <&spdif_dit6>;
cpu-dai-name = "I2S6";
codec-dai-name = "dit-hifi";
tx-mask = <0xFF>;
rx-mask = <0xFF>;
format = "dsp_a";
bitclock-inversion;
bit-format = "s16_le";
bclk_ratio = <4>;
srate = <8000>;
num-channel = <1>;
ignore_suspend;
name-prefix = "o";
status = "disabled";
};
nvidia,dai-link-7 {
link-name = "spdif-dit-7";
cpu-dai = <&tegra_dmic1>;
codec-dai = <&spdif_dit7>;
cpu-dai-name = "DMIC1";
codec-dai-name = "dit-hifi";
format = "i2s";
bit-format = "s16_le";
srate = <48000>;
ignore_suspend;
num-channel = <2>;
name-prefix = "a";
status = "disabled";
};
nvidia,dai-link-8 {
link-name = "spdif-dit-8";
cpu-dai = <&tegra_dmic2>;
codec-dai = <&spdif_dit8>;
cpu-dai-name = "DMIC2";
codec-dai-name = "dit-hifi";
format = "i2s";
bit-format = "s16_le";
srate = <48000>;
ignore_suspend;
num-channel = <2>;
name-prefix = "b";
status = "disabled";
};
nvidia,dai-link-9 {
link-name = "spdif-dit-9";
cpu-dai = <&tegra_dmic3>;
codec-dai = <&spdif_dit9>;
cpu-dai-name = "DMIC3";
codec-dai-name = "dit-hifi";
format = "i2s";
bit-format = "s16_le";
srate = <48000>;
ignore_suspend;
num-channel = <2>;
name-prefix = "c";
status = "disabled";
};
nvidia,dai-link-10 {
link-name = "spdif-dit-10";
cpu-dai = <&tegra_dmic4>;
codec-dai = <&spdif_dit10>;
cpu-dai-name = "DMIC4";
codec-dai-name = "dit-hifi";
format = "i2s";
bit-format = "s16_le";
srate = <48000>;
ignore_suspend;
num-channel = <2>;
name-prefix = "d";
status = "disabled";
};
dspk_1_dai_link: nvidia,dai-link-11 {
link-name = "dspk-playback-r";
cpu-dai = <&tegra_dspk1>;
codec-dai = <&spdif_dit11>;
cpu-dai-name = "DSPK1";
codec-dai-name = "dit-hifi";
format = "i2s";
bit-format = "s16_le";
srate = <48000>;
num-channel = <2>;
ignore_suspend;
name-prefix = "d1";
status = "disabled";
};
dspk_2_dai_link: nvidia,dai-link-12 {
link-name = "dspk-playback-l";
cpu-dai = <&tegra_dspk2>;
codec-dai = <&spdif_dit12>;
cpu-dai-name = "DSPK2";
codec-dai-name = "dit-hifi";
format = "i2s";
bit-format = "s16_le";
srate = <48000>;
num-channel = <2>;
ignore_suspend;
name-prefix = "d2";
status = "disabled";
};
};
I modified the above code, is it still necessary to modify other files?
Thanks