Adding pcie peripherals to Orin NX with JP6

Autonomous Machines Jetson & Embedded Systems Jetson Orin NX
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1

We have a custom carrier board for Orin NX with RTL8111 on PCIE port 3 and M2 PCIe module on PCIE port 2. I have enables C7 and C9, and changed ODMDATA to 9 in p3767.conf.common

I am using p3509-a02-p3767-0000.conf to flash the board. This file references p3768-0000-p3767-0000-a0.conf which specifies the device tree file tegra234-p3768-0000+p3767-0000-nv.dtb. I also set TBCDTB_FILE=“${DTB_FILE}” to remove DTB from UEFI.
I checked pinmux and all the signals are correct by default.

I have followed the developer guide but I am stuck at how to define the PHY node. The developer guide shows example as follows;

Configuration Option 2 (Device Tree)

pcie@141e0000 { /* C7x1 node */
    status = "okay";
    phys = <&p2u_gbe_0>;
    phy-names = "p2u-0";
};

pcie@140c0000 { /* C9x1 */
    status = "okay";
    phys = <&p2u_gbe_1>;
    phy-names = "p2u-0";
};

and when I add this to the C7 and C9 PCIe controller nodes I get this error when recompiling the dts

"ERROR (phandle_references): /bus@0/pcie@141e0000: Reference to non-existent node or label “p2u_gbe_0”

The developer guide references this file to edit pcie in sources but it does not exist in sources or file system.

“pipe2uphy DT nodes are defined in SoC DT at $(TOP)/hardware/nvidia/soc/t234/kernel-dts/tegra234-soc/tegra234-soc-pcie.dtsi”

So I am decompiling the tegra234-p3768-0000+p3767-0000-nv.dtb, editing the dts, and recompiling to dtb.

Without making the phy changes, it recompiles and I can flash the device and I can see the peripherals in lspci, but I do not get an IP address to the RTL8111 , which appears as Eth1 in ifconfig on the device.

Can you tell me how to edit the phy nodes correctly.

3

The original device tree already provided a overlay to enable C7 and C9. You should read it first.

4

Can you provide a link to the document has this information that I should read first.

5

tegra234-p3767-sku-handling.dtsi

6

I could not find any file called tegra234-p3767-sku-handling.dtsi in latest jetpack 6 (jetson-linux-r3640).

There is an overlay specified in p3768-0000-p3767-0000-a0.conf which is

OVERLAY_DTB_FILE+=“,tegra234-p3768-0000+p3767-0000-dynamic.dtbo”

inside this file it specifies pcie node overlays for C7 and C9

so is there anything that needs to be edited to get PCIe ports 2 and 3 to work in the latest jetpack 6 on a custom carrier board.

7

For every Jetson, the source code are public source code tarball that you should download from our website… you won’t find it in the BSP directory.

8

I am saying that I dont find this file in the repo for jetson-linux-r3640

These are the files downloaded and extracted

Jetson_Linux_R36.4.0_aarch64.tbz2
Tegra_Linux_Sample-Root-Filesystem_R36.4.0_aarch64.tbz2
public_sources.tbz2

using these extraction commands for public sources

tar xjf public_sources.tbz2
cd Linux_for_Tegra/source
tar xjf kernel_src.tbz2

Is there some other download I am missing ?

9

NVIDIA kernel dts files are inside of kernel_oot_modules_src.tbz2

10

Thanks Wayne, can you direct me to the procedure for applying this dsti

11

I am not asking you to apply this dtsi directly. I am just telling that this dtsi has an example to enable C7 and C9.

12

When I use the C7 and C9 details in example file tegra234-p3767-sku-handling.dtsi and add to overlay file tegra234-p3768-0000+p3767-0000-dynamic.dtbo then I get these errors.

Is there another step required to add the missing references …

overlay.dts:57.39-61.27: ERROR (phandle_references): /p3767-sku-handling-fragment@6/overlay/pcie@141e0000: Reference to non-existent node or label “p2u_gbe_0”

overlay.dts:64.39-70.27: ERROR (phandle_references): /p3767-sku-handling-fragment@6/overlay/pcie@140c0000: Reference to non-existent node or label “vdd_1v8_ao”

overlay.dts:64.39-70.27: ERROR (phandle_references): /p3767-sku-handling-fragment@6/overlay/pcie@140c0000: Reference to non-existent node or label “p2u_gbe_1”

13

You can just trace the code to find out where the reference is.

14

The references come from this file "tegra234-p3767-sku-handling.dtsi " for C7 and C9 configuration, specifically,

                    /* C7 */
                    pcie@141e0000 {
                            phys = <&p2u_gbe_0>;
                            phy-names = "p2u-0";
                            num-lanes = <1>;
                    };

                    /* C9 */
                    pcie@140c0000 {
                            status = "okay";
                            vddio-pex-ctl-supply = <&vdd_1v8_ao>;
                            phys = <&p2u_gbe_1>;
                            phy-names = "p2u-0";
                            num-lanes = <1>;

This is the same as the online developer guide example for editing pcie as per my original question. I was stuck at the same point which is why I asked this question.

Do I need to create these phandles p2u_gbe_1, p2u_gbe_0 , if so, is there a guide to what is required and how to implement it.

15

Trace more down to the code to find out where p2u_gbe_1 and p2u_gbe_0 are defined…

It is already defined somehwere. It just your code didn’t include that.

This is basic code tracing thing. There is no document needed for such easy thing…

17

@WayneWWW why not just answer the question? Wouldn’t that take as long as typing the responses you did already that offered zero help?

I think the required two nodes are in hardware/nvidia/t23x/nv-public/tegra234.dtsi:

as follows:


p2u_gbe_0: phy@3f20000 {

compatible = “nvidia,tegra234-p2u”;

reg = <0x0 0x03f20000 0x0 0x10000>;

reg-names = “ctl”;

#phy-cells = <0>;

};

p2u_gbe_1: phy@3f30000 {

compatible = “nvidia,tegra234-p2u”;

reg = <0x0 0x03f30000 0x0 0x10000>;

reg-names = “ctl”;

#phy-cells = <0>;

};

But let’s confirm that with the people here that are paid to help users. What do you think @WayneWWW ?