ADMAIF_AXBAR_TX<n>_FIFO_WRITE_0 Registers

Hello,
The ADMAIF_AXBAR_T/RX_FIFO_WRITE_0 Registers in the data manual are readable and writable.
But why is it not included it in the tegra210_admaif_wr_reg and tegra210_admaif_rd_reg of the tegra210_admaif_alt.c.
Can I read or write directly to ADMAIF_AXBAR_T/RX_FIFO_WRITE_0 registers without using dma?
Can the data I write directly into the ADMAIF_AXBAR_TX_FIFO_WRITE_0 register be transmitted through the i2s interface?

We only validate the ADMAIF by using the DMA to write/read to the ADMAIF XBAR FIFOs and so yes these registers are not listed in the list of registers that are handled by regmap. I don’t see why you could not read/write directly to these registers with the CPU and use the ADMAIF in the PIO mode. However, then you need to ensure you manage the FIFO correctly to avoid overruns and underruns.

Regards,
Jon

Hello,
That said, if I set ADMAIF to PIO mode, I can read or write to these registers?

Since there is still no data on i2s output data pin,I want to distinguish between the dma setting problem and the axbar problem by writing these register directly.

For the above problems, you told me to check register Settings, clock Settings and pin Settings.
For register Settings, I checked axbar,admaif,adma,i2s register,Do I need to check any other registers?
For the clock, I can verify that there is ahub,apb,i2s clk output by cat /sys/kernel/debug/clk/clk_summary,do I need to confirm any other clocks?

One more question,The following error occurs when I execute the tegra210_xbar_runtime_resume function,do I need to do any other configuration before executing this function?

CPU3: SError detected, daif=1c0, spsr=0x200000c5, mpidr=80000101, esr=bf40c000
Unhandled ExceptExc pniEn3.
x33 
        3x =    00x000300003000a984
x[   26.189904] CPU0: SError detected, daif=1c0, spsr=0x800000c5, mpidr=80000100, esr=bf000002
0 [   26.189910] CPU4: SError detected, daif=1c0, spsr=0x200000c5, mpidr=80000102, esr=bf40c000
=               0x[   26.189935] **************************************
00000[   26.189940] CPU0 Machine check error in AXI2APB@0x23b0000:
00[   26.189947] Raw FIFO Entry: 0
0000[   26.189949]      ADDR: 0x42900800
0[   26.189951]         STAT: 0x11048249
00[   26.189953] --------------------------------------
0[   26.189955] Decoded FIFO Entry: 0
0[   26.189957]         Direction: WRITE
0
0[   26.189959]         Bridge ID: 0x9
1 [   26.189962]        Error Type: 0x12 -- Timeout error
=       [   26.189964]  Length: 0
        [   26.189967]  Protection: 0x2 -- Unprivileged, Non-Secure, Data Access
0[   26.189970]         Source ID: 0x1 -- CCPLEX
=[   26.189972]         AXI_ID: 0x4 -- A57 Core 0
0       [   26.189974]  Cache: 0x1 -- Device
0[   26.189976]         Burst: 0x1
x0[   26.189985]        Address: 0x2900800 -- /ahub + 0x0
0[   26.189987] **************************************
000000[   26.191691] **************************************
0[   26.191693] ROC:CCE Machine Check Error:
b[   26.191695] ROC:CCE Registers:
0[   26.191697]         STAT: 0xb400000000040413
1[   26.191699]         ADDR: 0x7

x2[   26.191700]        MSC1: 0x80ffc
 [   26.191702]         MSC2: 0x900000020000
b[   26.191703] --------------------------------------
0[   26.191705] Decoded ROC:CCE Machine Check:
        [   26.191706]  Uncorrected (this is fatal)

[   26.191708]  Error reporting enabled when error arrived
02[   26.191710]        Error Code = 0x413
0[   26.191713]         Destination Error
0       [   26.191717]  Command = CRdCleanInv (0x7)
00x80[   26.191719]     Address Type = Secure DRAM
8[   26.191767]         Address = 0x0 (Unknown Device)
00510[   26.191768]     TLimit = 0x3ff
8
 [   26.191770]         Poison Error Mask = 0x80
8[   26.191772]         More Info = 0x20000
0[   26.191773]         Timeout Info = 0x0
 [   26.191775]                 ART ID = 0x0
=[   26.191778]         Source = L2_1 (A57) (0x1)
        [   26.191780]  TID = 0x2

Thank you very much.

Hello,
I set ADMAIF to PIO mode and write to the ADMAIF_AXBAR_TX_FIFO_WRITE_0 register,now there’s data on the i2s output data pin.
So it should now be possible to determine that the adma configuration is at fault,not admaif,axbar or i2s.
One of my doubts is that there is no destination address register in the ADMA registers.The destination address of adma should be ADMAIF_AXBAR_TX_FIFO_WRITE_0 register address.Which register determines which ADMAIF_AXBAR_TX_FIFO_WRITE_0 adma moves data to.
Is it when I set the TX_REQUEST_SELECT bits of the ADMA_PAGE_CH_CTRL_0 register to 1, adma will move data to the ADMAIF_AXBAR_TX<1>_FIFO_WRITE_0 register.

Yes, according to the Tegra X2 TRM the programming guide for the ADMA states …

“Software should ensure AHUB_FIFO_CTRL_0_TX_FIFO_SIZE or AHUB_FIFO_CTRL_0_RX_FIFO_SIZE registers in
an ADMA channel and FIFO_CTRL_0_DMA_FIFO_SIZE register of AHUB channel mapped to this ADMA channel are programmed to the same value. ADMA and AHUB channel mapping is done through
CTRL_0_RX_REQUEST_SELECT or CTRL_0_TX_REQUEST_SELECT registers in ADMA.”

Regards,
Jon

Hello,
I did not configure the ADMA_PAGE_CH_AHUB_FIFO_CTRL_0 and ADMAIF_AXBAR_TX_FIFO_CTRL_0 registers,so the register value is the default value,that is AHUB_FIFO_CTRL_0_TX_FIFO_SIZE = FIFO_CTRL_0_DMA_FIFO_SIZE =3.
I checked the adma registers configuration and found that it should be correct. The following is the register value.Are there any errors about adma registers ? In addition to the registers of adma itself, which registers should I pay attention to?
The adma can interrupt at i2s clock frequency, but there is no data on the i2s output pin.

admareg[2930000] = 1
admareg[2930004] = 0
admareg[2930008] = 7
admareg[293000c] = 3
admareg[2930020] = 80800
admareg[293002c] = 0
admareg[2930030] = ff
admareg[2930034] = 0
admareg[2930038] = 0
admareg[293003c] = 0
admareg[2930050] = 0
admareg[2930054] = 0
admareg[2930058] = 0
admareg[293005c] = 0
admareg[2930070] = 1ffffff
admareg[2930074] = 0
admareg[2930078] = 0
admareg[293007c] = 0
admareg[2930084] = ffffff
admareg[2930088] = 0
admareg[293008c] = 0
admareg[2930090] = 0
admareg[2930098] = 0
admareg[293009c] = 0
admareg[29300a0] = 0
admareg[29300a4] = 0
admareg[29300a8] = 0
admareg[29300ac] = 0
admareg[29300b0] = 0
admareg[29300b4] = 0
admareg[29300b8] = 0
admareg[29300bc] = 0
admareg[29300c0] = 0
admareg[29300c4] = 0
admareg[29300c8] = 0
admareg[29300cc] = 0
admareg[29300d0] = 0
admareg[29300d4] = 0
admareg[29300d8] = 0
admareg[29300dc] = 0
admareg[29300e0] = 0
admareg[29300e4] = 0

admareg[2940000] = 1
admareg[2940004] = 0
admareg[294000c] = 1
admareg[2940010] = 0
admareg[2940018] = 0
admareg[294001c] = 0
admareg[2940024] = 8004202
admareg[2940028] = 30400081
admareg[294002c] = 1010303
admareg[2940030] = 7d0
admareg[2940034] = f2200000
admareg[2940038] = 0
admareg[294003c] = 0
admareg[2940040] = 0
admareg[2940044] = 7d0
admareg[2940048] = 0
admareg[2940054] = 0
admareg[2940058] = 0
admareg[294005c] = 0
admareg[2940060] = 0

Hello!

The above register setting looks odd to me. I think that ‘TARGET_MEMORY_BUFFERS’ field should be 0. Did you intend to set the ‘SOURCE_ADDR_WRAP’ to 8 words?

Is there any reason why you are not using the ADMA driver that is distributed with rel28.x? You should be able to use the dmaengine APIs from within your driver to use this driver. For Tegra X2 there is the ADAST that also needs to be configured you use the ADMA. See drivers/dma/tegra18x-adma.c.

Regards,
Jon

Hello!
admareg[2940028] = 30400081 mean that SOURCE_MEMORY_BUFFERS=3,TARGET_MEMORY_BUFFERS=0, SOURCE_ADDR_WRAP=TARGET_ADDR_WRAP=0.So this register value should be ok.

The reason why I use rel27.1 is that the kernel of rel28.x cannot start, I do not know the reason.But 27.1 also works.

I already used the dmaengine APIs.

substream->stream = SNDRV_PCM_STREAM_PLAYBACK,id=0,tranfer_data_size=2000
int  coinv_tegra_adma_init(struct snd_pcm_substream *substream,int id)
{
	struct dma_chan *chan;
	struct device *dev = admaif_device;
	struct dma_slave_config slave_config;
	struct dma_async_tx_descriptor *desc;
	struct tegra210_admaif *admaif = dev_get_drvdata(admaif_device);
	int ret;
	ptr_area = dma_alloc_writecombine(admaif_device,1024*640,&buf_addr,GFP_KERNEL);
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
		chan = dma_request_slave_channel(dev, "tx1");
		if (IS_ERR(chan)) {
			dev_err(dev, "dmaengine pcm open failed with err\n");
			return PTR_ERR(chan);
		}
		slave_config.direction = DMA_MEM_TO_DEV;
		slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
		slave_config.dst_addr = admaif->playback_dma_data[id].addr;
		slave_config.dst_maxburst = 8;
	}else {
		chan = dma_request_slave_channel(dev, "rx1");
		if (IS_ERR(chan)) {
			dev_err(dev, "dmaengine pcm open failed with err\n");
			return PTR_ERR(chan);
		}
		slave_config.direction = DMA_DEV_TO_MEM;
		slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
		slave_config.src_addr = admaif->capture_dma_data[id].addr;
		slave_config.src_maxburst = 8;
	}
	slave_config.slave_id = admaif->capture_dma_data[id].req_sel;
	ret = dmaengine_slave_config(chan, &slave_config);
	if (ret < 0) {
		dev_err(dev, "dma slave config failed with err %d\n", ret);
		return ret;
	}
	desc = dmaengine_prep_dma_cyclic(chan,
		buf_addr,
		tranfer_data_size * 4,
		tranfer_data_size, slave_config.direction, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
	if (!desc){
		dev_err(dev, "dmaengine_prep_dma_cyclic failed with err\n");
		return -ENOMEM;
	}
	desc->callback = dma_complete_callback;
	desc->callback_param = &slave_config;
	dmaengine_submit(desc);
	dma_async_issue_pending(chan);
	return 0;
}

I didn’t really notice tegra18x-adma.c.But tegra_adma_init is called automatically in the tegra_adma_runtime_resume function,so ADAST is already configured.I printed out the value of the ADAST register, which should be correct.
[ 52.867450] ADMA_AST_RGN_SLAVE_BASE_LO:40000001
[ 52.867450] ADMA_AST_RGN_SLAVE_BASE_HI:0
[ 52.867450] ADMA_AST_RGN_MASTER_BASE_LO:40000000
[ 52.867450] ADMA_AST_RGN_MASTER_BASE_HI:0
[ 52.867450] ADMA_AST_RGN_MASK_BASE_LO:1ffff000
[ 52.867450] ADMA_AST_RGN_MASK_BASE_HI:0
[ 52.867450] ADMA_AST_RGN_CONTOL:8008