ADV7280 for TX2 color bar

Hi

I’m trying to receive a color bar from 7280 on my TX2.
The ADV is configured to output 720x576 progressive, 50 Hz.

Mcamha_f@21 {
devnode = “video5”;
reg = <0x21>;
physical_w = “5.095”;
physical_h = “4.930”;
sensor_model = “helicam_adv7280”;
avdd-reg = “vana”;
dvdd-reg = “vdig”;
iovdd-reg = “dovdd”;
status = “okay”;
clocks = <0x10 0x5a>;
clock-names = “extperiph2”;
mclk = “extperiph2”;
reset-gpios = <0x29 0x5 0x0>;
vana-supply = <0x2a>;
vdig-supply = <0x2b>;
dovdd-supply = <0x28>;

		mode0 {
			mclk_khz = "24000";
			num_lanes = [31 00];
			tegra_sinterface = "serial_f";
			phy_mode = "DPHY";
			discontinuous_clk = "no";
			cil_settletime = [30 00];
			active_w = "720";
			active_h = "576";
			line_length = "1250";
			mclk_multiplier = "2.25 ";
			pix_clk_hz = "54000000";
			pixel_t = "yuv_yuyv";
			readout_orientation = [30 00];
			inherent_gain = [31 00];
			dpcm_enable = "false";
			gain_factor = "16";
			framerate_factor = "1000000";
			exposure_factor = "1000000";
			step_gain_val = [31 00];
			default_gain = "16";
			step_framerate = [31 00];
			default_framerate = "60000000";
			step_exp_time = [31 00];
			default_exp_time = "2495";y DTS is 

when i’m try to read data using GSTREAMER i receive

dmesg :

[ 1156.738767] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 1156.749619] nvcsi 150c0000.nvcsi: csi4_stream_check_status (5) INTR_STATUS 0x00000004
[ 1156.757626] nvcsi 150c0000.nvcsi: csi4_stream_check_status (5) ERR_INTR_STATUS 0x00000004
[ 1156.766083] nvcsi 150c0000.nvcsi: csi4_cil_check_status (5) CILA_INTR_STATUS 0x00000004
[ 1156.774362] nvcsi 150c0000.nvcsi: csi4_cil_check_status (5) CILA_ERR_INTR_STATUS 0x00000004
[ 1156.992231] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 1156.998786] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 1157.009700] nvcsi 150c0000.nvcsi: csi4_cil_check_status (5) CILA_INTR_STATUS 0x00000004
[ 1157.017900] nvcsi 150c0000.nvcsi: csi4_cil_check_status (5) CILA_ERR_INTR_STATUS 0x00000004
[ 1157.232408] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11

tracer log
sudo cat /sys/kernel/debug/tracing/trace | grep tag:

kworker/1:2-7723 [001] … 1157.848415: rtcpu_vinotify_event: tstamp:36535147704 tag:CHANSEL_PXL_SOF channel:0x00 frame:2 vi_tstamp:36535147203 data:0x00000001
kworker/1:2-7723 [001] … 1157.848422: rtcpu_vinotify_event: tstamp:36535147879 tag:ATOMP_FS channel:0x00 frame:2 vi_tstamp:36535147232 data:0x00000000
kworker/1:2-7723 [001] … 1157.848429: rtcpu_vinotify_event: tstamp:36535150118 tag:CHANSEL_LOAD_FRAMED channel:0x20 frame:2 vi_tstamp:36535149756 data:0x08000000
kworker/1:2-7723 [001] … 1157.848437: rtcpu_vinotify_event: tstamp:36535723464 tag:CHANSEL_PXL_EOF channel:0x00 frame:2 vi_tstamp:36535722785 data:0x023f0002
kworker/1:2-7723 [001] … 1157.848444: rtcpu_vinotify_event: tstamp:36535723617 tag:ATOMP_FE channel:0x00 frame:2 vi_tstamp:36535722830 data:0x00000000
kworker/1:2-7723 [001] … 1157.848451: rtcpu_vinotify_event: tstamp:36535732330 tag:CSIMUX_STREAM channel:0xff frame:0 vi_tstamp:36535731952 data:0x00100000
kworker/1:2-7723 [001] … 1157.904197: rtcpu_vinotify_event: tstamp:36536357078 tag:CSIMUX_STREAM channel:0xff frame:0 vi_tstamp:36536356689 data:0x00100000
kworker/1:2-7723 [001] … 1157.904208: rtcpu_vinotify_event: tstamp:36536981818 tag:CSIMUX_STREAM channel:0xff frame:0 vi_tstamp:36536981426 data:0x00100000
kworker/1:2-7723 [001] … 1157.904215: rtcpu_vinotify_event: tstamp:36537606549 tag:CSIMUX_STREAM channel:0xff frame:0 vi_tstamp:36537606162 data:0x00100000
kworker/1:2-7723 [001] … 1157.960160: rtcpu_vinotify_event: tstamp:36538231291 tag:CSIMUX_STREAM channel:0xff frame:0 vi_tstamp:36538230899 data:0x00100000
kworker/1:2-7723 [001] … 1157.960169: rtcpu_vinotify_event: tstamp:36538856025 tag:CSIMUX_STREAM channel:0xff frame:0 vi_tstamp:36538855636 data:0x00100000
kworker/1:2-7723 [001] … 1157.960186: rtcpu_vinotify_event: tstamp:36539480763 tag:CSIMUX_STREAM channel:0xff frame:0 vi_tstamp:36539480373 data:0x00100000
kworker/1:2-7723 [001] … 1158.016216: rtcpu_vinotify_event: tstamp:36540105497 tag:CSIMUX_STREAM channel:0xff frame:0 vi_tstamp:36540105109 data:0x00100000
kworker/1:2-7723 [001] … 1158.016233: rtcpu_vinotify_event: tstamp:36540730236 tag:CSIMUX_STREAM channel:0xff frame:0 vi_tstamp:36540729846 data:0x00100000
kworker/1:2-7723 [001] … 1158.016241: rtcpu_vinotify_event: tstamp:36541354971 tag:CSIMUX_STREAM channel:0xff frame:0 vi_tstamp:36541354582 data:0x00100000
kworker/1:2-7723 [001] … 1158.072051: rtcpu_vinotify_event: tstamp:36541979707 tag:CSIMUX_STREAM channel:0xff frame:0 vi_tstamp:36541979319 data:0x00100000
kworker/1:2-7723 [001] … 1158.072160: rtcpu_vinotify_event: tstamp:36543269324 tag:CHANSEL_PXL_SOF channel:0x00 frame:1 vi_tstamp:36543268781 data:0x00000001

Thanks for help

hello oscar_fridman,

may I know which CSI port your sensor module were using, are you using port-F ?
you may also refer to Tegra X2 Series SoC Technical Reference Manual,
according to below errors, you got an error with intr_cil_data_lane_sot_mb_err0_a.

[ 1156.749619] nvcsi 150c0000.nvcsi: csi4_stream_check_status (5) INTR_STATUS 0x00000004
[ 1156.757626] nvcsi 150c0000.nvcsi: csi4_stream_check_status (5) ERR_INTR_STATUS 0x00000004
[ 1156.766083] nvcsi 150c0000.nvcsi: csi4_cil_check_status (5) CILA_INTR_STATUS 0x00000004
[ 1156.774362] nvcsi 150c0000.nvcsi: csi4_cil_check_status (5) CILA_ERR_INTR_STATUS 0x00000004
[ 1156.992231] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11

there’s no definition of yuv_yuyv pixel format types,
please also access L4T sources to check kernel sources.
please have a try to report it as yuv_yuyv16
for example,
$L4T_Sources/r32.4.3/Linux_for_Tegra/source/public/kernel/nvidia/drivers/media/platform/tegra/camera/sensor_common.c

static int extract_pixel_format(
        const char *pixel_t, u32 *format)
{
...
        else if (strncmp(pixel_t, "yuv_yuyv16", size) == 0)
                *format = V4L2_PIX_FMT_YUYV;