ADV7280m configuration

17600810981 · March 13, 2020, 2:43am

Hello Shane,

There is my dmesg log:

[ 1096.536661] to_state:443
[ 1096.536703] adv7280_s_power:530
[ 1096.536708] adv7280_set_power:498 on = 1
[ 1096.536711] I2C WRITE 4 @f
[ 1096.536895] I2C WRITE 2 @de
[ 1096.537030] I2C WRITE f7 @d2
[ 1096.537164] I2C WRITE 65 @d8
[ 1096.537297] I2C WRITE 9 @e0
[ 1096.537487] I2C WRITE 0 @2c
[ 1096.537916] I2C WRITE 0 @0
[ 1096.539358] nvcsi 150c0000.nvcsi: phy mode unavailable in props, use default
[ 1096.539365] nvcsi 150c0000.nvcsi: csi_port: 0
[ 1096.540498] to_state:443
[ 1096.540502] adv7280_g_input_status:451
[ 1096.540505] adv7280_read:324
[ 1096.540745] adv7280_read:324
[ 1096.540926] __adv7280_status:420 status1 = 0xf
[ 1096.540929] __adv7280_status:421 vid_sel = 0x4
[ 1096.540932] adv7280_status_to_v4l2:408
[ 1096.540934] status = 0
[ 1096.540937] RET = 0
[ 1096.540940] status = 0
[ 1096.544829] tegra-vi4 15700000.vi: Create Surface with imgW=720, imgH=480, memFmt=203
[ 1096.566838] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=1
[ 1096.566844] nvcsi 150c0000.nvcsi: csi4_stream_init
[ 1096.566854] nvcsi 150c0000.nvcsi: csi4_stream_config
[ 1096.566862] nvcsi 150c0000.nvcsi: csi4_stream_config (0) read VC0_DPCM_CTRL = 00000000
[ 1096.566865] nvcsi 150c0000.nvcsi: settle time reading from of_node
[ 1096.566871] nvcsi 150c0000.nvcsi: discontinuous_clk = 0 from of_node
[ 1096.566873] nvcsi 150c0000.nvcsi: phy mode unavailable in props, use default
[ 1096.566875] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 1096.566880] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[ 1096.566887] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 102
[ 1096.566889] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[ 1096.566892] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 25
[ 1096.566900] to_state:443
[ 1096.566902] adv7280_s_stream:960
[ 1096.566904] adv7280_read:324
[ 1096.567069] adv7280_read:324
[ 1096.567228] __adv7280_status:420 status1 = 0xd
[ 1096.567231] __adv7280_status:421 vid_sel = 0x4
[ 1096.570954] video4linux video0: vi_notify_wait: vi4 got SOF syncpt buf[ffffffc1e0836800]
[ 1096.586223] tegra-vi4 15700000.vi: Status:  4 channel:00 frame:0001
[ 1096.592508] tegra-vi4 15700000.vi:      timestamp sof 1108307762176 eof 1108323013280 data 0x01e00040
[ 1096.601736] tegra-vi4 15700000.vi:      capture_id 1 stream  0 vchan  0
[ 1096.792811] tegra-vi4 15700000.vi: PXL_SOF syncpt timeout! err = -11
[ 1096.799289] tegra-vi4 15700000.vi: tegra_channel_error_recovery: attempting to reset the capture channel
[ 1096.809154] nvcsi 150c0000.nvcsi: csi4_stop_streaming port_idx=0, lanes=1
[ 1096.809162] nvcsi 150c0000.nvcsi: settle time reading from of_node
[ 1096.809172] nvcsi 150c0000.nvcsi: discontinuous_clk = 0 from of_node
[ 1096.809178] nvcsi 150c0000.nvcsi: phy mode unavailable in props, use default
[ 1096.809182] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 1096.809190] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000001
[ 1096.809199] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[ 1096.809235] nvcsi 150c0000.nvcsi: csi4_cil_check_status 404
[ 1096.809263] nvcsi 150c0000.nvcsi: csi4_start_streaming port_idx=0, lanes=1
[ 1096.809268] nvcsi 150c0000.nvcsi: csi4_stream_init
[ 1096.809284] nvcsi 150c0000.nvcsi: csi4_stream_config
[ 1096.809297] nvcsi 150c0000.nvcsi: csi4_stream_config (0) read VC0_DPCM_CTRL = 00000000
[ 1096.809301] nvcsi 150c0000.nvcsi: settle time reading from of_node
[ 1096.809309] nvcsi 150c0000.nvcsi: discontinuous_clk = 0 from of_node
[ 1096.809325] nvcsi 150c0000.nvcsi: phy mode unavailable in props, use default
[ 1096.809330] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 1096.809337] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000000
[ 1096.809354] nvcsi 150c0000.nvcsi: cil core clock: 204, csi clock: 102
[ 1096.809361] nvcsi 150c0000.nvcsi: cil_settingtime was autocalculated
[ 1096.809366] nvcsi 150c0000.nvcsi: csi settle time: 33, cil settle time: 25
[ 1096.809777] tegra-vi4 15700000.vi: Create Surface with imgW=720, imgH=480, memFmt=203
[ 1096.810482] to_state:443
[ 1096.810493] adv7280_s_stream:960
[ 1096.810510] nvcsi 150c0000.nvcsi: csi4_stop_streaming port_idx=0, lanes=1
[ 1096.810515] nvcsi 150c0000.nvcsi: settle time reading from of_node
[ 1096.810525] nvcsi 150c0000.nvcsi: discontinuous_clk = 0 from of_node
[ 1096.810529] nvcsi 150c0000.nvcsi: phy mode unavailable in props, use default
[ 1096.810534] nvcsi 150c0000.nvcsi: csi4_phy_config
[ 1096.810542] nvcsi 150c0000.nvcsi: NVCSI_CIL_CONFIG = 00000001
[ 1096.810551] nvcsi 150c0000.nvcsi: csi4_stream_check_status
[ 1096.810558] nvcsi 150c0000.nvcsi: csi4_stream_check_status (0) ERROR_STATUS2VI_VC0 = 0x00000004
[ 1096.819467] nvcsi 150c0000.nvcsi: csi4_cil_check_status 404
[ 1096.828303] to_state:443
[ 1096.828311] adv7280_s_power:530
[ 1096.828317] adv7280_set_power:498 on = 0
[ 1096.828322] I2C WRITE 24 @f
[ 1096.828497] I2C WRITE 80 @0

According with TRM: ERROR_STATUS2VI_VC0 = 0x00000004 means the CRC check failed:
28.6.58 NVCSI_STREAM_0_ERROR_STATUS2VI_VC0_0
This error status will be sent to VI. Set by hardware, automatically cleared at next SOF pulse. This is the RO register for
software.
Offset: 0x4025 | Byte Offset: 0x10094 | Read/Write: RO | Secure: TrustZone Protected | Reset: 0x00000000

Bit    Reset  Description
3:0    0x0    err_status2vi_vc0:
              [0]: PP FSM timeout error
              [1]: PH ECC single bit error
              [2]: Packet Payload CRC error
              [3]: Packet Payload is less than WC in PH

There’s some other modification can I do to disable the CRC?

Hi alfredosalvarani.It seems you’ve got the same situation as I said before:“I’m facing a similar problem.By changing the mask registers I’ve solved some problem, but remaining an error: csi4_channel_check_status (2) ERROR_STATUS2VI_VC0 = 0x00000004.”
It turned out to be a capture device configuration problem, a missing of EOT(end of transmission) signal.