After enabling spi1 in the device tree, the self-loopback test of spidev_test failed

shl1994539341 · January 15, 2026, 2:23am

Hello, when using the third-party carrier board, I needed to enable SPI1. So I modified the device tree.

	spi@c260000 {
		iommus = <0x03 0x04>;
		#address-cells = <0x01>;
		dma-coherent;
		clock-names = "spi\0pll_p\0osc";
		nvidia,clk-parents = "pll_p\0osc";
		resets = <0x02 0x5c>;
		interrupts = <0x00 0x25 0x04>;
		clocks = <0x02 0x88 0x02 0x5e 0x02 0x5b>;
		#size-cells = <0x00>;
		spi-max-frequency = <0x3dfd240>;
		dma-names = "rx\0tx";
		compatible = "nvidia,tegra186-spi";
		status = "okay";
		reg = <0x00 0xc260000 0x00 0x10000>;
		phandle = <0x38f>;
		dmas = <0x05 0x10 0x05 0x10>;
		reset-names = "spi";

		spi@0 {
			compatible = "tegra-spidev";
			reg = <0x00>;
			spi-max-frequency = <0x2faf080>;
			controller-data {
				nvidia,enable-hw-based-cs;
				nvidia,tx-clk-tap-delay = <0x00>;
				nvidia,rx-clk-tap-delay = <0x10>;
			};
		};

		prod-settings {
			#prod-cells = <0x04>;

			prod {
				prod = <0x00 0x194 0x80000000 0x00>;
			};
		};
	};

In the /dev directory, it can be seen that SPI1 has been enabled successfully and spi@0 has been added successfully.

Then I ran the “spidev_test” program. It could be seen that spi0 passed the test, but spi1 did not receive any data.

How to troubleshoot the problem

shl1994539341 · January 15, 2026, 2:26am

root@ayxx-desktop:/home/ayxx/spitest/spidev-test-master# dmesg | grep spi
[ 14.419466] spi-tegra114 3210000.spi: Adding to iommu group 2
[ 14.436885] spi-tegra114 c260000.spi: Adding to iommu group 2
[ 14.454077] spi-tegra114 3230000.spi: Adding to iommu group 2
root@ayxx-desktop:/home/ayxx/spitest/spidev-test-master#

KevinFFF · January 15, 2026, 3:21am

Hi shl1994539341,

You can refer to https://elinux.org/Jetson/L4T/peripheral/#Mapping for their mapping.

The spi@c260000 is from SPE, do you short MISO and MOSI externally?

shl1994539341 · January 15, 2026, 3:50am

I confirmed that I had made a short circuit, and I measured it with an oscilloscope. When I was conducting the test, the waveform of the clock signal did not appear.

shl1994539341 · January 15, 2026, 3:53am

My device tree was obtained by decompiling from devic-tree, modified, then recompiled and replaced. I would like to confirm if this approach is feasible.

KevinFFF · January 15, 2026, 6:52am

Please note that the level of this SPI is 1V8 rather than 3V3.
It should work if you have enabled it from the device tree.

Have you configured its pinmux before the verification?
Please also share the full dmesg for further check.

shl1994539341 · January 15, 2026, 7:13am

I’m certain it’s 1.8V. We used a level converter that converts 1.8V to 3.3V. We also adopted the same approach in SPI0.

I have sent my dmesg. Thank you.

dmsgOrinAGX.txt (69.9 KB)

shl1994539341 · January 15, 2026, 7:19am

KevinFFF · January 16, 2026, 2:28am

[   14.293609] spi-tegra114 3210000.spi: Adding to iommu group 2
[   14.302196] spi-tegra114 c260000.spi: Adding to iommu group 2
[   14.306704] spi-tegra114 3230000.spi: Adding to iommu group 2

Okay, 3 SPI interfaces have been probed correctly.

Could you get a scope to measure if there’s any signal output from MOSI after you run spidev_test tool?

Please also check if removing the following lines can help for your case.

	spi@c260000 {
		iommus = <0x03 0x04>;
		#address-cells = <0x01>;
-		dma-coherent;
		clock-names = "spi\0pll_p\0osc";
		nvidia,clk-parents = "pll_p\0osc";
		resets = <0x02 0x5c>;
		interrupts = <0x00 0x25 0x04>;
		clocks = <0x02 0x88 0x02 0x5e 0x02 0x5b>;
		#size-cells = <0x00>;
		spi-max-frequency = <0x3dfd240>;
-		dma-names = "rx\0tx";
		compatible = "nvidia,tegra186-spi";
		status = "okay";
		reg = <0x00 0xc260000 0x00 0x10000>;
		phandle = <0x38f>;
-		dmas = <0x05 0x10 0x05 0x10>;
		reset-names = "spi";
		..

shl1994539341 · January 16, 2026, 3:46am

I have commented out these contents, but there is an error message in dmesg.

After that, I removed these comments and recompiled.

When I was compiling the device tree, there were the following errors regarding spi@c260000.

current_system.dts:9170.9-9179.5: Warning (spi_bus_bridge): /spi@c260000/spi@0: incorrect #size-cells for SPI bus

current_system.dts:9159.3-44: Warning (clocks_property): /spi@c260000:clocks: cell 0 is not a phandle reference

current_system.dts:9159.3-44: Warning (clocks_property): /spi@c260000:clocks: cell 2 is not a phandle reference

current_system.dts:9159.3-44: Warning (clocks_property): /spi@c260000:clocks: cell 4 is not a phandle reference

current_system.dts:9167.3-32: Warning (dmas_property): /spi@c260000:dmas: cell 0 is not a phandle reference

current_system.dts:9167.3-32: Warning (dmas_property): /spi@c260000:dmas: cell 2 is not a phandle reference

current_system.dts:9152.3-24: Warning (iommus_property): /spi@c260000:iommus: cell 0 is not a phandle reference

current_system.txt (551.5 KB)

I submitted the device tree that I decompiled.

KevinFFF · January 19, 2026, 5:21am

I still see dma related properties included in spi@c260000 node.

	spi@c260000 {
		iommus = <0x03 0x04>;
		#address-cells = <0x01>;
		dma-coherent;
		clock-names = "spi\0pll_p\0osc";
		nvidia,clk-parents = "pll_p\0osc";
		resets = <0x02 0x5c>;
		interrupts = <0x00 0x25 0x04>;
		clocks = <0x02 0x88 0x02 0x5e 0x02 0x5b>;
		#size-cells = <0x00>;
		spi-max-frequency = <0x3dfd240>;
		dma-names = "rx\0tx";
		compatible = "nvidia,tegra186-spi";
		status = "okay";
		reg = <0x00 0xc260000 0x00 0x10000>;
		phandle = <0x38f>;
		dmas = <0x05 0x10 0x05 0x10>;
		reset-names = "spi";

Please also help to check if you’ve configured the pinmux for this SPI interface correctly.
The expected pinmux configuration should be like the following:

shl1994539341 · January 20, 2026, 3:42am

I added the Pinmux settings and the SPI2 settings to the decompiled dtc file. After recompiling and replacing it, the SPI2 can now be used.

		exp-header-pinmux {
			phandle = <0x560>;

			hdr40-pin24 {
				nvidia,tristate = <0x00>;
				nvidia,function = "spi1";
				nvidia,enable-input = <0x01>;
				nvidia,pins = "spi1_cs0_pz6";
			};

			hdr40-pin12 {
				nvidia,tristate = <0x01>;
				nvidia,function = "rsvd3";
				nvidia,enable-input = <0x00>;
				nvidia,pins = "soc_gpio41_ph7";
			};

			hdr40-pin40 {
				nvidia,tristate = <0x01>;
				nvidia,function = "rsvd3";
				nvidia,enable-input = <0x00>;
				nvidia,pins = "soc_gpio42_pi0";
			};

			hdr40-pin19 {
				nvidia,tristate = <0x00>;
				nvidia,function = "spi1";
				nvidia,enable-input = <0x01>;
				nvidia,pins = "spi1_mosi_pz5";
			};

			hdr40-pin35 {
				nvidia,tristate = <0x01>;
				nvidia,function = "rsvd3";
				nvidia,enable-input = <0x00>;
				nvidia,pins = "soc_gpio44_pi2";
			};

			hdr40-pin23 {
				nvidia,tristate = <0x00>;
				nvidia,function = "spi1";
				nvidia,enable-input = <0x01>;
				nvidia,pins = "spi1_sck_pz3";
			};

			hdr40-pin21 {
				nvidia,tristate = <0x00>;
				nvidia,function = "spi1";
				nvidia,enable-input = <0x01>;
				nvidia,pins = "spi1_miso_pz4";
			};

			hdr40-pin38 {
				nvidia,tristate = <0x01>;
				nvidia,function = "rsvd3";
				nvidia,enable-input = <0x00>;
				nvidia,pins = "soc_gpio43_pi1";
			};

			hdr40-pin26 {
				nvidia,tristate = <0x00>;
				nvidia,function = "spi1";
				nvidia,enable-input = <0x01>;
				nvidia,pins = "spi1_cs1_pz7";
			};

			spi2_sck_pcc0 {
				nvidia,pins = "spi2_sck_pcc0";
				nvidia,function = "spi2";
				nvidia,tristate = <0x00>;
				nvidia,enable-input = <0x01>;
			};

			spi2_miso_pcc1 {
				nvidia,pins = "spi2_miso_pcc1";
				nvidia,function = "spi2";
				nvidia,tristate = <0x00>;
				nvidia,enable-input = <0x01>;
			};

			spi2_mosi_pcc2 {
				nvidia,pins = "spi2_mosi_pcc2";
				nvidia,function = "spi2";
				nvidia,tristate = <0x00>;
				nvidia,enable-input = <0x01>;
			};

			spi2_cs0_pcc3 {
				nvidia,pins = "spi2_cs0_pcc3";
				nvidia,function = "spi2";
				nvidia,tristate = <0x00>;
				nvidia,enable-input = <0x01>;
			};
		};

Also, I would like to ask how I should use the three files generated by using Orin_Jetson_Series_Pinmux_Config_Template-v2.1. Do I need to replace certain files in the bsp source code and recompile them in order to use them? Thank you

KevinFFF · January 20, 2026, 6:32am

Yes, you have to replace them in BSP package and reflash the board to apply the change. Please note that they are loaded in early boot stage(MB1) so the reflashing is required.
You can refer to Jetson AGX Orin Platform Adaptation and Bring-Up — NVIDIA Jetson Linux Developer Guide for details.

This approach should be fine as the pinctrl driver will also configure the pinmux during boot up.

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After enabling spi1 in the device tree, the self-loopback test of spidev_test failed

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