After tuning HDMI register , which driver file should I modify?

Robotics & Edge Computing Jetson & Embedded Systems Jetson Orin NX
1

Jetson Linux 36.3 + ORIN NX
referenced to <Jetson-Orin-Nano-NX-Series-Modules-Tuning-Complinace-Guide_DA-11267-001v1.1.pdf> , I used devmem2 command to tune HDMI register. and found out the correct register value.
After tuning HDMI register , which driver file should I modify to set this register?
using devmem2 command ,every time I plug out / plugin HDMI cable, the register is set to the wrong value.

2

The address of register I would like to set are: 0x1380c038 and 0x1380c120

4

Could anyone help?
I don’t think calling “devmem2 register w val” every time I plug in / out hdmi cable is a good idea.

5

please check dcb-tool.

https://docs.nvidia.com/jetson/archives/r35.6.0/DeveloperGuide/SD/Kernel/DisplayConfigurationAndBringUp/OrinDisplayconfig.html?highlight=dcb%20tool#dcb-tool

6

There are some much config items in TMDS/DP setting,
Could you tell my which item could config (0x1380c038 and 0x1380c120) register?

======================================================
| DCB TOOL |

| Enter 0 => Show Input DCB |
| Enter 1 => Modify DCB |
| Enter 2 => Show modified DCB |
| Enter 3 => Show TMDS settings |
| Enter 4 => Show DP settings |
| Enter 5 => Modify TMDS settings |
| Enter 6 => Show modified TMDS settings |
| Enter 7 => Modify DP settings |
| Enter 8 => Show modified DP settings |
| Enter 9… => Exit |

image
image505×126 14.5 KB

image
image680×518 50.4 KB

7

TMDS setting is for HDMI

8

Can not find SOR_LANE_PREEMPHASIS_0(0x1380c120) or SOR_PLL_SPARE_0(0x1380c038) in TMDS settings
DCB TOOL

image
image451×185 2.78 KB

->Enter 5 => Modify TMDS settings →
image

9

DCB tool could only modify the follow 7 items(registers) .
How can I modify 0x1380c120 and 0x1380c038 ?
image

10

let me check and go back to you.

11

Hi,

TMDS setting shall have these. Could you try to configure it?

==============================================================================
Link 0 LinkInfo table header offset = 0x113d
==============================================================================
TMDS info DispMacro Info Table Link A
==============================================================================
==============================================================================
TMDS info DispMacro Info Table Link Rate 340_plus_entry
==============================================================================
	 DispMacroLinkRateInfoEntryLinkRate - 34001
	 DispMacroLinkRateInfoEntrySORICHPM - 0x5
	 DispMacroLinkRateInfoEntrySORFilter - 0xa
	 DispMacroLinkRateInfoEntrySORVCOCAP - 0x0
	 DispMacroLinkRateInfoEntrySORLoadAdjust - 0x0
	 DispMacroLinkRateInfoEntrySORTXPULinkValue - 0x6
	 DispMacroLinkRateInfoEntrySORSelTimer - 0x3
	 DispMacroLinkRateInfoEntrySORTXBias - 0x0
	 DispMacroLinkRateInfoEntrySORLaneDriveCurrent Sublink 0 - 0x3a3f3e3d
	 DispMacroLinkRateInfoEntrySORLaneDriveCurrent Sublink 1 - 0x0
	 DispMacroLinkRateInfoEntrySORLanePreEmphasis Sublink 0 - 0x5050505
	 DispMacroLinkRateInfoEntrySORLanePreEmphasis Sublink 1 - 0x0
	 DispMacroLinkRateInfoEntrySORLanePreshoot Sublink 0 - 0x0
	 DispMacroLinkRateInfoEntrySORCustomSetting - 0x245888
	 DispMacroLinkRateInfoEntrySORPllSpareWrite - 0x0
15

image
image1196×485 22.7 KB

What is the meaning of "165_340_Entry "?
Does it means “HDMI clock between 165MHz to 340MHz” ?

16

This topic was automatically closed 14 days after the last reply. New replies are no longer allowed.