AGX Orin C5 NVHS PCIe RC-EP tvnet: R36.4.3 stuck Polling.Compliance (0x2018); works on JP5.1.3

Robotics & Edge Computing Jetson Systems Jetson AGX Orin
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Summary: Dual custom AGX Orin SoC-to-SoC C5 x8 tvnet. Same hardware works on JP5.1.3 (R35). JP6.2 / R36.4.3 mostly fails training; occasional link-up then fatal AER Surprise Down after ~80s. EP LTSSM APPL_DEBUG 0x2018 = Polling.Compliance; RC reports Phy link never came up.

Platform: A=RC (pcie@141a0000, nvhs-uphy-config-0), B=EP (pcie-ep@141a0000, nvhs-uphy-config-1). Shared REFCLK (non-SRNS). UEFI TBCDTB disables C5 RC on both boards; Linux FDT still enables C5 RC on A. Configfs start=1 before rebooting RC.

Ruled out: ODMDATA/DT role error, boot ordering, PERST# integrity (scoped 0→3.3 V on B_PEX_L5_RST_N), UEFI enumeration, link-speed downgrade. Configfs start 0/1 does not re-init PHY; PERST# does.

Logs:
RC: Phy link never came up; 10de:229a bridge then bus released; no 10de:2296.
EP: LTSSM state: 0x2018 timeout -110 (Polling.Compliance, (0x2018 & 0x1F8)>>3 = 3).
Intermittent: link up ~80s then SDES; tvnet AER: can’t recover (no error_detected callback).
Additional: A C5 also fails NVMe training. REFCLK not measured with a differential probe yet.

Questions:

  1. Typical causes for Polling.Compliance 0x2018 on Orin C5 NVHS EP in R36.4.3?
  2. Regression R35 → R36 on the same hardware?
  3. Is a longer RC link-wait supported for SoC EP on JP6?
  4. New pinmux requirements for C5 EP (pex_l5_rst_n_paf1 input) enforced in R36?

Please advise register dumps, REFCLK/PERST timing checks, or known R36 C5 EP issues. Full logs/DTS/PERST scope plots available.

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A_syslog_C5_linkup_then_SDES.txt (4.7 KB)

Attachment 1: A (RC) — C5 Phy link never came up, 10de:229a then bus released.

RC
RC1184×639 152 KB

Attachment 2: B (EP) — start=1, 10de:2296, LTSSM 0x2018 Polling.Compliance.

EP
EP940×607 136 KB

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Is it possible to validate rel-36.5? We just tested that on rel-36.5 last week and saw no issue.

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Update: resolved on our side.

Root cause was a wrong logic-level configuration (active-high vs active-low) of the PCIe sideband pins between the two Orin boards. RC and EP did not agree on the pin polarity, so link training never completed reliably.

@WayneWWW thanks for suggesting rel-36.5. We did not need a newer release for this case; aligning the pin levels between RC and EP was enough.