AGX Orin : GPIO definitions for 40-pin header

Autonomous Machines Jetson & Embedded Systems Jetson AGX Orin
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1

Looks like the same GPIO is used for different pins:

ag@fufu:kernel# grep TEGRA_AON_GPIO ./hardware/nvidia/soc/tegra/kernel-include/dt-common/jetson/tegra234-p3737-0000-p3701-0000.h
#define HDR40_PIN16_GPIO        TEGRA_AON_GPIO(BB, 0)
#define HDR40_PIN29_GPIO        TEGRA_AON_GPIO(AA, 1)
#define HDR40_PIN31_GPIO        TEGRA_AON_GPIO(AA, 0)
#define HDR40_PIN32_GPIO        TEGRA_AON_GPIO(BB, 1)
#define HDR40_PIN33_GPIO        TEGRA_AON_GPIO(AA, 3) <== !!!
#define HDR40_PIN37_GPIO        TEGRA_AON_GPIO(AA, 3) <== !!!

Is this intentional or a typo?

It’s not the case on other platforms, e.g. Xavier

ag@fufu:kernel# grep TEGRA_AON_GPIO ./hardware/nvidia/soc/tegra/kernel-include/dt-common/jetson/tegra194-p2888-0001-p2822-0000.h
#define HDR40_PIN16_GPIO        TEGRA_AON_GPIO(BB, 0)
#define HDR40_PIN29_GPIO        TEGRA_AON_GPIO(AA, 3)
#define HDR40_PIN31_GPIO        TEGRA_AON_GPIO(AA, 2)
#define HDR40_PIN32_GPIO        TEGRA_AON_GPIO(BB, 1)
#define HDR40_PIN33_GPIO        TEGRA_AON_GPIO(AA, 0)
#define HDR40_PIN37_GPIO        TEGRA_AON_GPIO(AA, 1)
3

hello Agtonomy,

the GPIO allocations has changed since kernel-5.10,
please refer to developer guide, [Identifying the GPIO Number]. please follow the GPIO debugfs for looking up the port and offset.
for example, 454 is the GPIO number of PQ.06

$ sudo cat /sys/kernel/debug/gpio | grep PQ.06
gpio-454 (PQ.06 )
4

The pinmux spreadsheet shows:

CAN0_DOUT	GP17_CAN0_DOUT	GPIO3_PAA.00	can0_dout_paa0	CAN0_DOUT	GPIO_PAA0	40-pin header Pin 31
CAN0_DIN	GP18_CAN0_DIN	GPIO3_PAA.01	can0_din_paa1	CAN0_DIN	GPIO_PAA1	40-pin header Pin 29
CAN1_DOUT	GP19_CAN1_DOUT	GPIO3_PAA.02	can1_dout_paa2	CAN1_DOUT	GPIO_PAA2	40-pin header Pin 33
CAN1_DIN	GP20_CAN1_DIN	GPIO3_PAA.03	can1_din_paa3	CAN1_DIN	GPIO_PAA3	40-pin header Pin 37

So this is indeed a typo, except it doesn’t look like these defines are used anywhere.

6

hello Agtonomy,

thanks for point-out, it indeed a typo. I’ve initial a code-review for code integration.

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