Agx orin multi pcie config

Robotics & Edge Computing Jetson Systems Jetson AGX Orin
1

pex_l1:

PCIE0_CLKREQ_N ->PEX_L1_CLKREQ_N，bidirectional
PCIE0_RST_N ->PEX_L1_RST_N,output
PCIE_WAKE_N ->PEX_WAKE_N,input

UPHY0_TX2_P ->UPHY_TX20_P
UPHY0_TX2_N ->UPHY_TX20_N
UPHY0_RX2_P ->UPHY_RX20_P
UPHY0_RX2_N ->UPHY_RX20_N
PCIE0_CLK_P ->PEX_CLK1_P
PCIE0_CLK_N ->PEX_CLK1_N

pex_l3:

PCIE10_CLKREQ_N ->PEX_L3_CLKREQ_N,
PCIE10_RST_N ->PEX_L3_RST_N
PCIE_WAKE_N ->->PEX_WAKE_N

UPHY2_TX4_P ->UPHY_TX6_P,
UPHY2_TX4_N ->UPHY_TX6_N
UPHY2_RX4_P ->UPHY_RX6_P
UPHY2_RX4_N ->UPHY_RX6_N
PCIE10_CLK_P ->PEX_CLK3_P
PCIE10_CLK_N ->PEX_CLK3_N

pex_l0:
PCIE7_CLKREQ_N ->PEX_L0_CLKREQ_N
PCIE7_RST_N ->PEX_L0_RST_N
PCIE_WAKE_N->PEX_WAKE_N

PCIE7_CLK_P ->PEX_CLK0_P
PCIE7_CLK_N ->PEX_CLK0_N
UPHY2_RX0_P ->UPHY_RX2_P
UPHY2_RX0_N ->UPHY_RX2_N
UPHY2_TX0_P ->UPHY_TX2_P
UPHY2_TX0_N ->UPHY_TX2_N

pex_l2:
PCIE8_CLKREQ_N ->PEX_L2_CLKREQ_N
PCIE8_RST_N ->PEX_L2_RST_N
PCIE_WAKE_N ->PEX_WAKE_N

PCIE8_CLK_P ->PEX_CLK2_P
PCIE8_CLK_N → PEX_CLK2_N
UPHY2_TX2_P ->UPHY_TX4_P
UPHY2_TX2_N ->UPHY_TX4_N
UPHY2_RX2_P ->UPHY_RX4_P
UPHY2_RX2_N ->UPHY_RX4_N

I want to configure the four groups above as PCIe, but I can’t find any entries for those balls in the “Orin_Jetson_Series_Pinmux_Config_Template-v2.1.xlsm” spreadsheet.
How should I modify the configuration?

3

*** Please note that this reply is generated by LLM automatically ***

Based on the provided information, it appears that you are trying to configure the PCIe lanes on the Jetson AGX Orin module. The PCIe lanes are controlled by the pinmux configuration, which is typically done using the OrinJetsonSeriesPinmuxConfigTemplatev21xlsm spreadsheet.

To configure the four groups of PCIe lanes (pexl0, pexl1, pexl2, and pexl3) as PCIe, you will need to modify the pinmux configuration in the spreadsheet. Here are the steps to follow:

  1. Open the OrinJetsonSeriesPinmuxConfigTemplatev21xlsm spreadsheet and navigate to the “Pinmux Configuration” sheet.
  2. Locate the rows corresponding to the PCIe lanes you want to configure (pexl0, pexl1, pexl2, and pexl3).
  3. In the “Pinmux Mode” column, select “PCIe” as the mode for each of the PCIe lanes.
  4. In the “Pinmux Configuration” column, select the corresponding PCIe configuration for each lane. For example, for pexl0, you might select “PCIe0” as the configuration.
  5. Make sure to update the “Pinmux Configuration” column for all four PCIe lanes (pexl0, pexl1, pexl2, and pexl3).
  6. Save the changes to the spreadsheet.

If you are unable to find the entries for the PCIe lanes in the spreadsheet, it is possible that they are not included in the template. In this case, you may need to add the PCIe lanes manually to the spreadsheet.

To add the PCIe lanes manually, follow these steps:

  1. Open the OrinJetsonSeriesPinmuxConfigTemplatev21xlsm spreadsheet and navigate to the “Pinmux Configuration” sheet.
  2. Insert new rows for each of the PCIe lanes you want to configure (pexl0, pexl1, pexl2, and pexl3).
  3. In the “Pin Name” column, enter the name of the PCIe lane (e.g. “pexl0”).
  4. In the “Pinmux Mode” column, select “PCIe” as the mode for each of the PCIe lanes.
  5. In the “Pinmux Configuration” column, select the corresponding PCIe configuration for each lane. For example, for pexl0, you might select “PCIe0” as the configuration.
  6. Make sure to update the “Pinmux Configuration” column for all four PCIe lanes (pexl0, pexl1, pexl2, and pexl3).
  7. Save the changes to the spreadsheet.

After modifying the pinmux configuration, you will need to recompile the device tree and update the firmware on the Jetson AGX Orin module.

It’s worth noting that the pinmux configuration can be complex and requires careful attention to detail. If you are unsure about any aspect of the configuration, it is recommended to consult the Jetson AGX Orin documentation or seek assistance from a qualified engineer.

In comparison to other Jetson modules, the pinmux configuration for the Jetson AGX Orin module is similar, but with some differences in the specific pin assignments and configurations. The Jetson TX2, for example, has a different pinmux configuration template, and the PCIe lanes are controlled by different pinmux modes and configurations.

In summary, to configure the four groups of PCIe lanes on the Jetson AGX Orin module, you will need to modify the pinmux configuration in the OrinJetsonSeriesPinmuxConfigTemplatev21xlsm spreadsheet, either by updating the existing entries or adding new rows manually. After modifying the pinmux configuration, you will need to recompile the device tree and update the firmware on the module.

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4

As I already said, those pins simply do not appear anywhere in the Orin_Jetson_Series_Pinmux_Config_Template-v2.1.xlsm spreadsheet—there is no row I can select or edit for them.

5

please refer to this table in the design guide document.

image
image612×778 74.4 KB

Only above controllers are supported on Orin AGX.

Some of the PCIe you mentioned in your list are not supported. For example,
PCIE10_CLKREQ_N ->PEX_L3_CLKREQ_N,
PCIE10_RST_N ->PEX_L3_RST_N

These are for C10 which is not present on Orin AGX.

UPHY_RX20/TX20 are also for a USB to use but not PCIe.

You should review your design with design guide document first…

8

If I can use C4 as one lane PCIe controler?

PCIe x1 (C4), RP

And, use UPHY_RX10/TX10 Lane 6 as the one lane?

9

你如果要使用C4當作一個x1 使用的話只能用uphy0 Lane 4或Lane7.

10

My hardeare clk is E23:PCIE4_CLK_P/E22:PCIE4_CLK_N, lane is B12:UPHY0_RX6_P/B13:UPHY0_RX6_N/K13:UPHY0_TX6_P/K12:UPHY0_TX6_N.

And the lspci’s log is 0004:01:00.0 Ethernet controller: Intel Corporation I210 Gigabit Unprogrammed (rev 03).

That’s possible? I’m confused.

11

We don’t guarantee that would really work fine because it is actually still a x4 setting in software.

So assume it shall start from UPHY0_TX4. Also, as reversed hardware is supported, it could also start with TX7.

12

There exist two I210 phy chip in my hardware, another connection is clk F24:PCIE5_CLK_P/F25:PCIE5_CLK_N,
lane D24:UPHY1_RX0_P/D25:UPHY1_RX0_N/H24:UPHY1_TX0_P/H25:UPHY1_TX0_N.

But, the pcie c5 is not recognized with the lspci? Maybe the driver software isn’t configured properly?

13

There is no update from you for a period, assuming this is not an issue anymore.
Hence, we are closing this topic. If need further support, please open a new one.
Thanks ~0107

How is the rst pin connected for your C5?

C5 software is already enabled in the default device tree.