AGX Orin PCIe FPGA Endpoint Not Enumerating on JetPack 35.1

Robotics & Edge Computing Jetson Systems Jetson AGX Orin
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1

Dear NVIDIA Team,

We are using Jetson AGX Orin (P3737 carrier board), connecting our FPGA to the M.2 Key‑M NVMe slot (PCIe C5 port, pcie@141a0000).

Key Background & Configuration

  1. FPGA side (Vivado 2018.3):
    • PCIe IP only supports PCIe Gen2 (5.0GT/s, Vivado 2018 limitation)
    • Enabled: PCIe to DMA Interface
    • Disabled: PCIe to AXI Lite Master Interface (no BAR0 AXI‑Lite register BAR configured)
    • Maximum link speed matched to Gen2
  2. Host side:
    • RK3588 host works perfectly: FPGA is detected normally via PCIe, link up and functional
    • Orin AGX M.2 slot works for NVMe SSD (SSD is detected normally)
  3. Observed status on AGX Orin:
    • PCIe physical layer reports :Link Up successfully
    • But `lspci` shows no FPGA device output at all
    • No PCIe enumeration happens after link up

Our Question:
Why does Orin AGX C5 (M.2) PCIe root port fail to enumerate our Gen2 FPGA, even with physical link up?
We have confirmed the FPGA works well on RK3588 Gen2 PCIe host, and Orin M.2 slot works for NVMe SSD.

We need official guidance on:

  1. Required PCIe device‑tree settings for Orin C5 port to enumerate Gen2‑only FPGA endpoint
  2. Whether Orin PCIe root port has special limitations for Gen2 endpoint without AXI‑Lite BAR0
  3. Root cause of link‑up‑but‑no‑enumeration issue on Orin M.2 slot

Thanks for your support.

2

*** Please note that this reply is generated by LLM automatically ***

Based on the provided context, I will attempt to provide a comprehensive answer to the question.

The issue described is related to the Jetson AGX Orin P3737 carrier board’s M2 KeyM NVMe slot PCIe C5 port, which is not enumerating a Gen2-only FPGA endpoint despite a successful physical link up.

To address this issue, let’s break down the requirements and potential limitations:

  1. Required PCIe devicetree settings for Orin C5 port to enumerate Gen2-only FPGA endpoint:

The devicetree settings for the PCIe C5 port on the Jetson AGX Orin module are not explicitly mentioned in the provided context. However, it is essential to ensure that the devicetree settings are correctly configured to support Gen2-only FPGA endpoints.

In general, the devicetree settings for PCIe on the Jetson AGX Orin module are defined in the tegra194-pcie.dtsi file. The pcie@141a0000 node, which corresponds to the PCIe C5 port, should be configured to support Gen2 speeds.

Here’s an example of how the devicetree settings might look:

pcie@141a0000 {
    compatible = "nvidia,tegra194-pcie";
    reg = <0x0 0x141a0000 0x0 0x1000>;
    #address-cells = <3>;
    #size-cells = <2>;
    device_type = "pci";
    bus-range = <0x00 0xff>;
    ranges = <0x81000000 0x0 0x14120000 0x0 0x20000 0x0 0x20000>;

    // Configure PCIe C5 port to support Gen2 speeds
    pcie@0 {
        reg = <0x0 0x141a0000 0x0 0x1000>;
        #address-cells = <3>;
        #size-cells = <2>;
        device_type = "pci";
        bus-range = <0x00 0xff>;
        ranges = <0x81000000 0x0 0x14120000 0x0 0x20000 0x0 0x20000>;
        speed = <2>; // Configure PCIe C5 port to support Gen2 speeds
    };
};
  1. Orin PCIe root port limitations for Gen2 endpoint without AXILite BAR0:

The provided context does not explicitly mention any limitations of the Orin PCIe root port for Gen2 endpoints without AXILite BAR0. However, it is essential to note that the Orin PCIe root port might have specific requirements or limitations for enumerating Gen2-only FPGA endpoints.

In general, the Orin PCIe root port is designed to support a wide range of PCIe devices, including those with AXILite BAR0. However, the specific requirements for enumerating Gen2-only FPGA endpoints might vary depending on the device and the system configuration.

  1. Root cause of link-up-but-no-enumeration issue on Orin M2 slot:

The root cause of the link-up-but-no-enumeration issue on the Orin M2 slot is likely related to the devicetree settings or the PCIe root port limitations. To troubleshoot this issue, it is recommended to:

  • Verify the devicetree settings for the PCIe C5 port to ensure that they are correctly configured to support Gen2 speeds.
  • Check the PCIe root port limitations for Gen2 endpoints without AXILite BAR0.
  • Ensure that the FPGA endpoint is correctly configured and functional.

In comparison to the RK3588 host, which works perfectly with the FPGA, the Orin AGX M2 slot might have specific requirements or limitations that need to be addressed. It is essential to consult the official documentation and seek guidance from NVIDIA to resolve this issue.

In summary, to enumerate a Gen2-only FPGA endpoint on the Orin AGX M2 slot, it is crucial to:

  • Verify the devicetree settings for the PCIe C5 port.
  • Check the PCIe root port limitations for Gen2 endpoints without AXILite BAR0.
  • Ensure that the FPGA endpoint is correctly configured and functional.

Official guidance from NVIDIA is necessary to resolve this issue, and it is recommended to consult the official documentation and seek support from NVIDIA to ensure that the Orin AGX M2 slot is correctly configured to support Gen2-only FPGA endpoints.

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4

Theoretically, the link speed will be automatically negotiated, and I noticed that the maximum speed written for the C5 port is Gen4 with no other restrictions.

5

Which Jetpack version are you trying to use here exactly?

6

There is no such thing called Jetpack35.1… Jetpack only has Jetpack5,6,7…

If you are talking about “l4t 35.1”, then I would say please try to upgrade your version because no one should really use that version in 2026 now.

7

Thank you for your advice.