AGX Orin RGMII always unplugged

[Wilson_Lin]

Hi Nvidia,

I’m using Marvell 88E1512 Phy on AGX Orin.
I have mainly referred to the following links and documents.

JP6.1 Orin AGX Custom Board ETH Phy 88E1512

Hi, I am trying to make the PHY 88E1512 RGMII work. After studying posts like this and this and the official JP6.1 documentation, I do not see any issues in the configuration. I can confirm that the correct pinmux configured correctly is in effect as I wrote it in the flashing conf file, the nodes in the device tree are configured correctly, the phy_reset GP5 is High, all the mgbe are disabled. The PHY and link works only in “serdes” mode with fixed-link node present (so I would exclude any h…

Currently, I can see Ethernet in the Settings, but it always shows as unplugged.

pnmux

                        eqos_txc_pe0 {
                                nvidia,pins = "eqos_txc_pe0";
                                nvidia,function = "eqos";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };

                        eqos_td0_pe1 {
                                nvidia,pins = "eqos_td0_pe1";
                                nvidia,function = "eqos";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };

                        eqos_td1_pe2 {
                                nvidia,pins = "eqos_td1_pe2";
                                nvidia,function = "eqos";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };

                        eqos_td2_pe3 {
                                nvidia,pins = "eqos_td2_pe3";
                                nvidia,function = "eqos";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };

                        eqos_td3_pe4 {
                                nvidia,pins = "eqos_td3_pe4";
                                nvidia,function = "eqos";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };

                        eqos_tx_ctl_pe5 {
                                nvidia,pins = "eqos_tx_ctl_pe5";
                                nvidia,function = "eqos";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };

                        eqos_rd0_pe6 {
                                nvidia,pins = "eqos_rd0_pe6";
                                nvidia,function = "eqos";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };

                        eqos_rd1_pe7 {
                                nvidia,pins = "eqos_rd1_pe7";
                                nvidia,function = "eqos";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };

                        eqos_rd2_pf0 {
                                nvidia,pins = "eqos_rd2_pf0";
                                nvidia,function = "eqos";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };

                        eqos_rd3_pf1 {
                                nvidia,pins = "eqos_rd3_pf1";
                                nvidia,function = "eqos";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };

                        eqos_rx_ctl_pf2 {
                                nvidia,pins = "eqos_rx_ctl_pf2";
                                nvidia,function = "eqos";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };

                        eqos_rxc_pf3 {
                                nvidia,pins = "eqos_rxc_pf3";
                                nvidia,function = "eqos";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };

                        eqos_sma_mdio_pf4 {
                                nvidia,pins = "eqos_sma_mdio_pf4";
                                nvidia,function = "eqos";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                        };

                        eqos_sma_mdc_pf5 {
                                nvidia,pins = "eqos_sma_mdc_pf5";
                                nvidia,function = "eqos";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                        };

                        soc_gpio17_pg4 {
                                nvidia,pins = "soc_gpio17_pg4";
                                nvidia,function = "rsvd0";
                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                        };

                        soc_gpio18_pg5 {
                                nvidia,pins = "soc_gpio18_pg5";
                                nvidia,function = "rsvd0";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                        };

dtsi

                ethernet@2310000 {
                        status = "okay";
                        phy-mode = "rgmii-id";
                        phy-handle = <&phy>;

                        nvidia,phy-reset-gpio = <&gpio TEGRA234_MAIN_GPIO(G, 5) 0>;

                        nvidia,mac-addr-idx = <0>;
                        nvidia,skip_mac_reset = <0>;
                        nvidia,mdio_addr = <0>;
                        nvidia,pause_frames = <0>;

                        mdio {
                                compatible = "nvidia,eqos-mdio";
                                #address-cells = <1>;
                                #size-cells = <0>;

                                phy: phy@0 {
                                        reg = <0>;
                                        nvidia,phy-rst-pdelay-msec = <224>; /* msec */
                                        nvidia,phy-rst-duration-usec = <10000>; /* usec */
                                        interrupt-parent = <&gpio>;
                                        interrupts = <TEGRA234_MAIN_GPIO(G, 4) IRQ_TYPE_LEVEL_LOW>;
                                        marvell,copper-mode;
                                        /* Setup LED[2] as interrupt pin (active low) */
                                        marvell,reg-init = <0x03 0x12 0x7fff 0x880>;
                                };
                        };
                };

$ cat /proc/interrupts | grep eth
202:          1          0          0          0          0          0          0          0     GICv3 226 Level     eth0.common_irq
203:          0          0          0          0          0          0          0          0     GICv3 218 Level     eth0.vm0
204:          0          0          0          0          0          0          0          0     GICv3 219 Level     eth0.vm1
205:          0          0          0          0          0          0          0          0     GICv3 220 Level     eth0.vm2
206:          0          0          0          0          0          0          0          0     GICv3 221 Level     eth0.vm3
304:          0          0          0          0          0          0          0          0  2200000.gpio  39 Level     2310000.ethernet:00

dmesg
dmesg.log (64.2 KB)

[velorin0]

Hi,
Does it show “Unplugged” even when you plug the cable??

[Wilson_Lin]

Hi velorin0,

Yes, it always shows as “unplugged,” regardless of whether I have connected the network cable or not.

[velorin0]

OK, I just wanted to make sure as it was not immediately obvious from your first post. :)
I answered you because I saw that you referenced my post. As you probably already saw, the solution in my case was that I had to set the interrupt pin as gpio input in the MB1 BCT. If you did that and still does not work, then you will have to check the PHY MDIO address and use it in the the DT, and also to check if in your case you are using the same interrupt pin as in the documentation (PG4) or smth else. Otherwise could be a hardware issue.
Good luck!

[Wilson_Lin]

Thanks for reply,
Our hardware circuit follows the documentation and uses PG4 and PG5.
The PG4 pin is already as input gpio.

[Wilson_Lin]

Hi all,

In this case, I keep the orignal ethernet@2310000 settings in /nv-soc/tegra234-base-overlay.dtsi
Do I need to delete it or change some settings?

                ethernet@2310000 {
                        compatible = "nvidia,nveqos";
                        reg = <0x0 0x02310000 0x0 0x10000>,    /* EQOS Base Register */
                              <0x0 0x023D0000 0x0 0x10000>,    /* MACSEC Base Register */
                              <0x0 0x02300000 0x0 0x10000>;    /* HV Base Register */
                        reg-names = "mac", "macsec-base", "hypervisor";
                        interrupts = <0 194 0x4>,       /* common */
                                     <0 186 0x4>, /* vm0 */
                                     <0 187 0x4>, /* vm1 */
                                     <0 188 0x4>, /* vm2 */
                                     <0 189 0x4>, /* vm3 */
                                     <0 190 0x4>, /* MACsec non-secure intr */
                                     <0 191 0x4>; /* MACsec secure intr */
                        interrupt-names = "common", "vm0", "vm1", "vm2", "vm3",
                                          "macsec-ns-irq", "macsec-s-irq";
                        resets = <&bpmp TEGRA234_RESET_EQOS>,
                                 <&bpmp TEGRA234_RESET_EQOS_MACSEC>; /* MACsec non-secure reset */
                        reset-names = "mac", "macsec_ns_rst";
                        clocks = <&bpmp TEGRA234_CLK_PLLREFE_VCOOUT>,
                                 <&bpmp TEGRA234_CLK_EQOS_AXI>,
                                 <&bpmp TEGRA234_CLK_EQOS_RX>,
                                 <&bpmp TEGRA234_CLK_EQOS_PTP_REF>,
                                 <&bpmp TEGRA234_CLK_EQOS_TX>,
                                 <&bpmp TEGRA234_CLK_AXI_CBB>,
                                 <&bpmp TEGRA234_CLK_EQOS_RX_M>,
                                 <&bpmp TEGRA234_CLK_EQOS_RX_INPUT>,
                                 <&bpmp TEGRA234_CLK_EQOS_MACSEC_TX>,
                                 <&bpmp TEGRA234_CLK_EQOS_TX_DIVIDER>,
                                 <&bpmp TEGRA234_CLK_EQOS_MACSEC_RX>;
                        clock-names = "pllrefe_vcoout", "eqos_axi", "eqos_rx",
                                      "eqos_ptp_ref", "eqos_tx", "axi_cbb",
                                      "eqos_rx_m", "eqos_rx_input",
                                      "eqos_macsec_tx", "eqos_tx_divider",
                                      "eqos_macsec_rx";
#if TEGRA_IOMMU_DT_VERSION >= DT_VERSION_2
                        interconnects = <&mc TEGRA234_MEMORY_CLIENT_EQOSR>,
                                        <&mc TEGRA234_MEMORY_CLIENT_EQOSW>;
                        interconnect-names = "dma-mem", "write";
#endif
                        iommus = <&smmu_niso1 TEGRA234_SID_EQOS>;
                        nvidia,num-dma-chans = <8>;
                        nvidia,num-mtl-queues = <8>;
                        nvidia,mtl-queues = <0 1 2 3 4 5 6 7>;
                        nvidia,dma-chans = <0 1 2 3 4 5 6 7>;
                        nvidia,tc-mapping = <0 1 2 3 4 5 6 7>;
                        /* Residual Queue can be any valid queue except RxQ0 */
                        nvidia,residual-queue = <1>;
                        nvidia,rx-queue-prio = <0x2 0x1 0x30 0x48 0x0 0x0 0x0 0x0>;
                        nvidia,tx-queue-prio = <0x0 0x7 0x2 0x3 0x0 0x0 0x0 0x0>;
                        nvidia,rxq_enable_ctrl = <2 2 2 2 2 2 2 2>;
                        nvidia,vm-irq-config = <&eqos_vm_irq_config>;
                        //status = "disabled";
                        nvidia,dcs-enable = <0x1>;
                        nvidia,macsec-enable = <0>;
                        nvidia,pad_calibration = <0x1>;
                        /* pad calibration 2's complement offset for pull-down value */
                        nvidia,pad_auto_cal_pd_offset = <0x0>;
                        /* pad calibration 2's complement offset for pull-up value */
                        nvidia,pad_auto_cal_pu_offset = <0x0>;
                        nvidia,rx_riwt = <512>;
                        nvidia,rx_frames = <64>;
                        nvidia,tx_usecs = <256>;
                        nvidia,tx_frames = <5>;
                        nvidia,promisc_mode = <1>;
                        nvidia,slot_num_check = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
                        nvidia,slot_intvl_vals = <0x0 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D 0x7D>;
                        nvidia,ptp_ref_clock_speed = <208333334>;
                        nvidia,instance_id = <4>; /* EQOS instance */
                        nvidia,ptp-rx-queue = <3>;
                        pinctrl-names = "mii_rx_disable", "mii_rx_enable";
                        pinctrl-0 = <&eqos_mii_rx_input_state_disable>;
                        pinctrl-1 = <&eqos_mii_rx_input_state_enable>;
                        nvidia,dma_rx_ring_sz = <1024>;
                        nvidia,dma_tx_ring_sz = <1024>;
                        dma-coherent;
                };

[WayneWWW]

There is no update from you for a period, assuming this is not an issue anymore.
Hence, we are closing this topic. If need further support, please open a new one.
Thanks

More like pinmux issue to me. It looks like the PHY reset didn’t get toggle once?