AGX Xaiver Auto Power-On Option No MCU

In agx xaiver oem product design guide , For designs that will not have a power button but should power on when the main power supply is connected, the optional ACOK circuit shown in Figure 5-7 should be implemented and the ACOK_L signal pulled to GND. In Figure 5-7, when SN74LVC1G74 power on , SD is HIGH, CP is HIGH. D is HIGH, RD is LOW at beginning, and after 1ms ,5V_AO_PGD becomes HIGH, so RD becomes HIGH. Refer to the truth table of SN74LVC1G74,Q is always LOW. And ACOK output is always LOW, how does the circuitry work? I don’t understand , please explain how it works. Thanks.


Q is always LOW.

?? The signal CARRIER_PWR_ON (L62) will set the DFF Q by SD ?

Hi, this is validated, please follow it well to your design if necessary.

Thanks. And I want to know the usage of 240Ω and 0.47uF, Can you help me?

Q is LOW at beginning, and ACOK output is LOW . so in Figure 5.6, PB is low , after about 30ms ,EN becomes HIGH,and VIN_PWR_ON becomes HIGH. Then after about 90ms,in Figure 5.7, CARRIER_PWR_ON becomes HIGH, Q is HIGH , ACOK is HIGH. In Figure 5.6, PB is HIGH, CARRIER_PWR_ON is HIGH, VDDIN_PWR_BAD_N is HIGH, so PSHOLD is HIGH, and EN stays HIGH. Is my understanding correct?

Hi, for the design that replicates reference, please just follow the circuit design well as that had been validated.

The 240ohm and 0,47uF are the RC timing circuit.

Hi, Mr.Trumany,

If you don’t feel like answering the question, please keep silent.


Validated ? Circuit diagrams of this type are often misprinted.

The 240ohm and 0,47uF are the RC timing circuit

RC timing circuit? Isn’t it just only a low-pass filter.

Hi, Mr.chenxuhust

The funtionality of SRC0 is a little bit complexed. So please refer to its datasheet.

May be your understanding is correct.

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Hi k-hamada,

Thanks for your sharing.

  1. Can you please point out which part is misprinted?
  2. This RC is for timing delay, not for low-pass.

Thanks very much.

Hi, Mr. Tormany

  1. Can you point out which part is misprinted?

It just points out a common possibility, but does not say that there is a typographical error in this figure. The manufacturer’s recommended schematics are often wrong, so the advice to follow the instructions is simply not appropriate.

2.This RC is for timing delay, not for low-pass.

Then, please tell me the exact delay time. How many msec will it be? Is the output impedance of DFF taken into consideration?


Is the output impedance of DFF taken into consideration?

Sorry, DFF → MOS FET and pull-up resister.


I forgot to say one thing.
Please tell your nVidia hardware engineers that they need to find a better and more reliable power-on-reset IC.
Apparently, they are indifferent about the instability of the IC output when the power is turned on.


  1. If you found any misprinted part, please let us know, we’ll be very appreciated, if not, please do not use that to comment the validated design in guide which is the recommended to customer to replicate.
  2. The delay can be roughly calculated by RC value. The timing is not so strict, it is for the delay before asserting BUTTON_POWER_ON* so that the power supply is stable enough when power on.
  3. Have you met issue of POR IC? If so, please share detail information of your tests so that we can check if is necessary to do that. Thanks.

Hi, Mr.Trumany

  1. If you insist that nobody can complain to this circuit because it’s recommended by nVidia, please do whatever you want.
    However, I do not understand the attitude of not accepting questions about the operation of the circuit.

  2. A low-pass filter is attached to prevent chattering when the power is turned on. It is not an RC time constant circuit.

  3. Instead of using this circuit, I will find a suitable POR IC and use it. The POR IC manufacturer guarantees the operation when the power is turned on. Depending on the semiconductor used, this recommended circuit may change its stability when the power is turned on.

What I want to say is that this circuit may work, but it’s not well designed. And it’s the task of nVidia’s hardware engineers to present a good POR IC.


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We’d appreciate any suggestion and also have no problem to accept customer’s complain. In this case, we just hope to get more evidence of misprinted part or POR IC issue as you said. Thank you for the discussion. I will forward this to related team.

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