Agx xavier eqos to sja1105Q switch

Hello,
We replaced the original phy with Nxp SJA1105Q to expand Ethernet port
Basically this thread looks similar with our case
https://forums.developer.nvidia.com/t/about-xavier-eqos-mac-to-mac/124451
I checked switch driver ,it looks spi initialization is good.

I can see tx packet count increment both side (Agx and PC which connect to one slave port of switch), but no rx packet counting
and I try to ping between two slave port, not luck on ethernet working.
I wanna double check whether two slave port communication has nothing to do with Agx Xavier after switch is well configured with spi ,Am I right?

Any other debug hints?

Thanks a lot!

Actually, we don’t have experience with switch on SPI case. Many other users can share their experience here.

ok, I’m still debugging,
I found the following extran log in dmesg compared to original Agx xaviar system log. as I know we didn’t touch eqos driver.
and I don’t know what car reset here exactly mean, could you help figure out what might happen?
'/* issue CAR reset to device */
ret = hw_if->car_reset(pdata);
if (ret < 0) {
dev_err(&dev->dev, “Failed to reset MAC\n”);
return -ENODEV;
}

1 Like

@leexye

Would you mind to share your connection diagram to help understand your case?

I wanna double check whether two slave port communication has nothing to do with Agx Xavier after switch is well configured with spi ,Am I right?

Yes, if your SPI driver setup as expected, it should work and nothing required anymore from AGX Xavier side.

SCHEMATIC1 _ 33_Enet_Architectu.pdf (51.9 KB)

I attached schematic in pdf format,thanks for your response. @alanz

Pls also share the dts file.

ether_qos@2490000 {
		/* PTP_ref clock speed in MHz */
		nvidia,ptp_ref_clock_speed = <312500000>;
		/* rxq_enable_ctrl = <rx0 rx1 rx2 rx3>
		 * 0x0 = Not enabled, 0x1 = Enabled for AV
		 * 0x2 = Enabled for Legacy, 0x3 = Reserved
		 */
		nvidia,rxq_enable_ctrl = <2 2 2 2>;
		nvidia,queue_prio = <0 1 2 3>;

		nvidia,use_tagged_ptp;
		nvidia,ptp_dma_ch = <3>;

		nvidia,chan_napi_quota = <64 64 64 64>;
		nvidia,pause_frames = <0>; /*0=enable, 1=disable */
		nvidia,phy-reset-gpio = <&tegra_main_gpio TEGRA194_MAIN_GPIO(G, 5) 0>;
		nvidia,phy0-reset-gpio = <&tegra_main_gpio TEGRA194_MAIN_GPIO(T, 3) 0>;
		nvidia,phy1-reset-gpio = <&tegra_main_gpio TEGRA194_MAIN_GPIO(T, 5) 0>;
		nvidia,phy7-reset-gpio = <&tegra_main_gpio TEGRA194_MAIN_GPIO(S, 6) 0>;
		nvidia,phy-max-frame-size = <16>;	/* size in kbytes */
		nvidia,eth_iso_enable = <1>; /*0=enable, 1=disable */
		phy-mode = "rgmii-id";
		nvidia,eqos_auto_cal_config_0_reg = <0x20010103>;
		resets = <0x5 0x11>;
		reset-names = "eqos_rst";
		
		fixed-link {
			speed=<1000>;
			full-duplex;
		};

		mdio {
			compatible = "nvidia,eqos-mdio";
			#address-cells = <1>;
			#size-cells = <0>;

			phy0: ethernet-phy@0 {
				reg = <0>;
				interrupt-parent = <&tegra_main_gpio>;
				interrupts = <TEGRA194_MAIN_GPIO(T, 0) IRQ_TYPE_LEVEL_LOW>;
				nvidia,phy-reset-gpio = <&tegra_main_gpio TEGRA194_MAIN_GPIO(T, 3) 0>;
				marvell,copper-mode;
				/* Setup LED[2] as interrupt pin (active low) */
				marvell,reg-init = <0x03 0x12 0x7fff 0x880>;
			};

			phy1: ethernet-phy@1 {
				reg = <1>;
				interrupt-parent = <&tegra_main_gpio>;
				interrupts = <TEGRA194_MAIN_GPIO(T, 4) IRQ_TYPE_LEVEL_LOW>;
				nvidia,phy-reset-gpio = <&tegra_main_gpio TEGRA194_MAIN_GPIO(T, 5) 0>;
				marvell,copper-mode;
				/* Setup LED[2] as interrupt pin (active low) */
				marvell,reg-init = <0x03 0x12 0x7fff 0x880>;
			};

			phy7: ethernet-phy@7 {
				compatible = "ethernet-phy-ieee802.3-c45";
				reg = <0x7>;
				interrupt-parent = <&tegra_main_gpio>;
				interrupts = <TEGRA194_MAIN_GPIO(T, 6) IRQ_TYPE_LEVEL_LOW>;
				nvidia,phy-reset-gpio = <&tegra_main_gpio TEGRA194_MAIN_GPIO(S, 6) 0>;
				marvell,copper-mode;
				/* Setup LED[2] as interrupt pin (active low) */
				/* marvell,reg-init = <0x03 0x12 0x7fff 0x880>; */
			};

		};
	};
spi@3210000 {
		status = "okay";
		sja1105p@0 {
			compatible = "nxp,sja1105p-switch";
			firmware_name = "sja1105p-1_cfg.bin";
			spi-max-frequency = <12000000>;
			spi-cpha;
			reg = <0x0>;			

			port-0 {
				is-host = <0x0>;
				null-phy = <0x0>;
				phy-ref = <&phy7>;
				
			};

			port-1 {
				is-host = <0x0>;
				null-phy = <0x0>;
				phy-ref = <&phy0>;				
			};

			port-2 {
				is-host = <0x0>;
				null-phy = <0x0>;
				phy-ref = <&phy1>;
				
			};

			port-3 {
				is-host = <0x0>;
				null-phy = <0x1>;
				phy-ref = <0x0>;
			};


			port-4 {
				is-host = <0x1>;
				null-phy = <0x1>;
				phy-ref = <0x0>;
				rx-delay = < 810 >;
				tx-delay = < 810 >;
			};
		};

		spi@1 {
			compatible = "spidev";
			reg = <0x1>;
			spi-max-frequency = <33000000>;
			controller-data {
				nvidia,enable-hw-based-cs;
				nvidia,rx-clk-tap-delay = <0x11>;
			};
		};
	};