AGX Xavier GPIO43(pq.07) 引脚配置成输出时无法拉高?

AGX Xavier GPIO43(pq.07) 引脚配置成输出时无法拉高?

  1. 在配置GPIO43时,发现将该引脚配置成output并拉高,烧录后,系统显示为输出高,但是通过测量,引脚状态仍然为Low. 参考过 这个TOPIC,按照他的改动方法,仍然不成功,以下将我这边的配置贴上来:
    tegra-tztek-pinmux.dtsi & tegra-tztek-pinmux-gpio.dtsi
    soc_gpio43_pq7 {
    nvidia,pins = “soc_gpio43_pq7”;
    nvidia,function = “rsvd2”;
    nvidia,pull = <TEGRA_PIN_PULL_UP>;
    nvidia,tristate = <TEGRA_PIN_DISABLE>;
    nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
    nvidia,lpdr = <TEGRA_PIN_DISABLE>;

gpio-output-high = <

sudo cat /sys/kernel/debug/gpio | grep gpio-43
gpio-423 ( | phy_1-reset-pin ) out hi

sudo cat /sys/kernel/debug/tegra_pinctrl_reg |grep q7
Bank: 0 Reg: 0x2430038 Val: 0x00000022 → soc_gpio43_pq7

同时,当我们配置成gpio input时候,通过外部给与电压,可以在系统中查询到状态变化


This is the community feedback category, this should be posted in the Jetson AGX Xavier for support coverage.
I can move this topic over for you.

Tom K

hello guwen,

did you configure the pin through pinmux spreadsheets and re-flashing the board with new *.cfg file? could you please share your steps for reference, thanks

I burned the BCT cfg file with tegra19x-mb1-pinmux-p2888-0000-a04-p2822-0000-b01.cfg.
The steps what i used are as follows:

  1. Modify gpio43 (pq7) to the internal pull-up and output status in the pinmux spreadsheets file, and then click the generate button to generate three configuration files: tegra19x Jetson_ agx_ xavier-pinmux tegra19x-jetson_ agx_ Xavier GPIO default and tegra19x Jetson_ agx_ xavier-padvoltage-default。

  2. Copy these three files to flashtool / Linux_ for_ Tegra / kernel / pinmux / t19x / path, and then use the script to generate galen.cfg,

  3. Copy the value of the register in galen.cfg and overwrite flashtool / Linux_ for_ Values of corresponding registers in Tegra / bootloader / t186ref / BCT / tegra19x-mb1-pinmux-p2888-0000-a04-p2822-0000-b01.cfg file

  4. Burn BCT configuration file

  5. Start the machine and check the value of the corresponding register and the status of the corresponding pin.

hello guwen,

those steps looks correct, may I know which JetPack release version you’re working with?

Jetpack 4.4 (L4T release 32.4.3)

Meanwhile I set this pin as an internal pull-up output and write the value from the application layer. When writing 1, the measured voltage is only 0.2 ~ 0.3V. Is the internal driving capability of this pin poor? If not, how can pinmux be configured to ensure the strongest driving capability?

The figure shows my configuration mode。

tegra19x-mb1-pinmux-p2888-0000-a04-p2822-0000-b01.cfg file :

  1. pinmux.0x02430038 = 0x0000002a; # soc_gpio43_pq7: rsvd2, pull-up, tristate-disable, input-disable, io_high_voltage-enable, lpdr-disable
  2. pinmux.0x02430038 = 0x00000022; # soc_gpio43_pq7: rsvd2, tristate-disable, input-disable, io_high_voltage-enable, lpdr-disable

I have tested both of the above configurations

hello guwen,

there’s the level shift (U76), please see the P2822 schematic for detail.
you may also access applications note, 40-Pin Expansion Header GPIO Usage Considerations for reference,

Do you mean that the current IO (PQ7) pins cannot be directly output to the specified high level, so additional level shift chips are needed? Meanwhile, could you please provide a link to the schematic diagram of P2822?

Hi ,
The pin K56 GPIO19 is direct connect from Xavier to 88Q2112,The GPIO out used as rst# signal for 88Q2112 with out extend pull Up or Pull Down.we disconnect trace and we can’t driver The GPIO 19 pin high。

Have you tried to disconnect it from PCIe connector (removing R838 on devit carrier) and measure its level?

Hello, I use Xavier devit carrier to burn the JP4.4 system(sudo ./ jetson-xavier mmcblk0p1), and then check it after power-on, and follow the following steps in the application layer:

  1. cd /sys/class/gpio/

  2. echo 423 > export

  3. cd gpio423

  4. echo out > direction

  5. echo 1 > value

Then monitor the corresponding GPIO (PQ7) pin level. Although it is later pulled up, the voltage amplitude can only reach 2~3V.
Could you please confirm whether the pin has this defect?

There is no update from you for a period, assuming this is not an issue any more.
Hence we are closing this topic. If need further support, please open a new one.

Have you tried to disconnect it from PCIe connector (removing R838 on devit carrier) and measure its level?

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