AGX Xavier operation on custom carrier board boot failed

background: Jetpack4.5 custom carrier board
question:Excuse me, is this at CBOOT? When boot fails.

all boot log:

[0000.106] W> RATCHET: MB1 binary ratchet value 4 is too large than ratchet level 2 from HW fuses.
[0000.114] I> MB1 (prd-version:
[0000.120] I> Boot-mode: Coldboot
[0000.123] I> Chip revision : A02P
[0000.126] I> Bootrom patch version : 15 (correctly patched)
[0000.131] I> ATE fuse revision : 0x200
[0000.134] I> Ram repair fuse : 0x0
[0000.138] I> Ram Code : 0x2
[0000.140] I> rst_source : 0x0
[0000.143] I> rst_level : 0x0
[0000.146] I> Boot-device: eMMC
[0000.161] I> sdmmc DDR50 mode
[0000.165] W> No valid slot number is found in scratch register
[0000.171] W> Return default slot: _a
[0000.174] I> Active Boot chain : 0
[0000.177] I> Boot-device: eMMC
[0000.181] W> MB1_PLATFORM_CONFIG: device prod data is empty in MB1 BCT.
[0000.189] I> Temperature = 41500
[0000.192] W> Skipping boost for clk: BPMP_CPU_NIC
[0000.196] W> Skipping boost for clk: BPMP_APB
[0000.200] W> Skipping boost for clk: AXI_CBB
[0000.204] W> Skipping boost for clk: AON_CPU_NIC
[0000.208] W> Skipping boost for clk: CAN1
[0000.212] W> Skipping boost for clk: CAN2
[0000.216] I> Boot-device: eMMC
[0000.219] I> Boot-device: eMMC
[0000.229] I> Sdmmc: HS400 mode enabled
[0000.233] I> ECC region[0]: Start:0x0, End:0x0
[0000.237] I> ECC region[1]: Start:0x0, End:0x0
[0000.241] I> ECC region[2]: Start:0x0, End:0x0
[0000.245] I> ECC region[3]: Start:0x0, End:0x0
[0000.250] I> ECC region[4]: Start:0x0, End:0x0
[0000.254] I> Non-ECC region[0]: Start:0x80000000, End:0x100000000
[0000.260] I> Non-ECC region[1]: Start:0x0, End:0x0
[0000.264] I> Non-ECC region[2]: Start:0x0, End:0x0
[0000.268] I> Non-ECC region[3]: Start:0x0, End:0x0
[0000.273] I> Non-ECC region[4]: Start:0x0, End:0x0
[0000.278] E> FAILED: Thermal config

Not yet entering the cboot.

What stage is this? What caused the stop here?

Could you directly move the same module from your board to devkit and see if it can pass this stage?

It can work normally on the devkit

Then this is hardware design problem. Please review your design with the design guide.

In which source code to add print to test the hardware, there is a problem in that device. I only have the source code of kernel and CBOOT. You said it didn’t enter CBOOT. I don’t know which source code to debug,it is difficult to find the problem by comparing the design guidance

This part of source code is not public.

[0000.546] E> FAILED: Thermal config

I saw that the boot was stopped in “failed: thermal config”, and “failed: Memio rail config” will be printed after the normal process. May there be a problem in the hardware design, can you provide me with a direction?

Hi, the log does not provide much info about issue. You’d better to follow the checklist in product design guide to check your schematic design, or compare your board design to that of devkit (P2822) to find out the difference.

In the first box, I don’t understand what “module pins” are and what “w / SOC ram_code [1:0] strapping pins” are
In the second box, I don’t understand what “module pin” are and what “Boot strapping pin” are

I still can’t find the cause of the problem. Is there any better test method?

Have you compared your design to schematic of P2822? Please do that to find out the difference first.

Please check chapter 15.3 Strapping Pins in Design Guide for the instruction.

I found SN74LVC1G74.pdf, but the pin defined in this document is different from the design guidance.
Is this chip correct?

Design Guide


Please check with vendor for pin description if necessary, sometimes they are just name difference.

I have confirmed with the supplier TI. For the time being, there is only the document of the second picture. I just want to confirm that these two pictures are the same chip

It should be same since the part number is same.

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I encountered the same problem as you when designing, please search NEXPERIA 74LVC1G74DC,125, you will find the answer

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