I’m interested in designing a custom carrier board with an AGX Xavier. I also want to design it so that it is forward compatible with the AGX Orin. The purpose is specifically for PCIe, where there will be three 4-lane buses. My questions are as follows.
1. Single Node Network (SNN): Is it possible to use the AGX Xavier pins connected to the SNN nets for high-speed differential signals (PCIe), or are these pins just dead ends?
2. PCIe block partitioning: Is it possible to operate two separate x4 PCIe buses within a single x8 PCIE block? (e.g., via Pinmux and Device Tree customization)
3. AGX Orin USB 3.x, PCIe, UFS, and MGBE Mapping Options: Are the AGX Orin configurations limited to only the stated three options in the image above, or can they be further customized?
For question 3, actually the info is out of date. Only the first 2 configurations are supported. The 3rd one is not. Please let us know where did you get this info. It requires correction.
Thank you for responding. It appears that I was using an outdated version of the Jetson AGX Orin Series and Jetson AGX Xavier Series Interface Comparison and Migration (DA-10655-001_v1.1 | March 2022). I see that there are only 2 configurations listed in the newer version (DA-10655-001_v1.2 | June 2022). Your answers for questions 2 and 3 are very clear.
Do you have an answer for question 1? Are the NVHS1 pins connected to the SNN nets usable on AGX Xavier?