Apply Orin NX Tuning Complinace patches failed

We are attempting to apply the patches provided in the Jetson Orin NX Series/Orin Nano Series Tuning Compliance Guide DA-11267-001_v0.5.pdf to the L4T35.2.1 codebase. While the first patch, “319ad28.diff,” has been successfully applied, we are encountering difficulty with the second patch, “9b39010.diff.” Specifically, we are unable to locate the file “3701-0000-3737-0000-uphy.dtsi.” Do you have any suggestions for resolving this issue? These patches are necessary for conducting PCIe Compliance Testing.


That is for bpmp dtb. Please convert the bpmp dtb back to dts by using dtc tool and then add the patch.

There are too many bpmp dtb files under bootloader folder, could you tell me which bpmp dtb?

I don’t know. You could check the board config to find out which bpmp dtb is in use.

Or read your flash log to find it out.

We using the bootloader/tegra234-bpmp-3767-0000-a02-3509-a02.dtb file. And we concvet the dtb to dts , but we can’t apply the following sentense directly .

clock@pllnvhs {
clk-id = <TEGRA234_CLK_PLLNVHS>;
disable-spread = <1>;
clock@pllgbe {
clk-id = <TEGRA234_CLK_PLLGBE>;
disable-spread = <1>;

We can’t convert back to dtb file. Have any other solution ?



Please convert them back to hex value.


After applying the modified dtb file and using the ‘lspci’ command to check the PCI root port, we still can’t see the other PCI bus. Based on previous experience, in order to perform PCIe Compliance Testing, we need to be able to see all PCIe root ports.

$ lspci
0008:00:00.0 PCI bridge: NVIDIA Corporation Device 229c (rev a1)
0008:01:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 15)

Could you help to check the attached kernel log and dts files ? Thanks

kernel.log (72.7 KB)
tegra234-bpmp-3767-0000-a02-3509-a02.dts (200.6 KB)


I don’t quite understand what you are doing. Why are you enabling pcie C8 on Orin NX? We don’t support C8 as the design guide indicates.

Hi WayneWWW,
We want to check SI of PCIE(DATA and clock), PCIE port and clock need to always work, not to be powered down. This is the patch from the document Jetson_Orin_NX_Series_Orin_Nano_Series_Tuning_Complinace_Guide_DA-11267-001_v0.5 attemps to do: the patch for disabling power down.
If power down function is disabled, we should see the PCIE root ports which are not connected to a device are still shown by lspci. However, after the patch is implemented, the result is not as we supposed.
Please help to check how to disable power down of PCIE port.



Please add some debug print around the patch which disable the pcie disable power-down to make sure it is really applied.


We saw the all PCIE root port after modify this patch “319ad28.diff”.

pcie->disable_power_down = true;

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Looks like the document is wrong. Let us update it. Thanks for reporting this issue.

We have updated the Jetson AGX Orin Series Tuning and Compliance Guide Application Note.


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