Dear NVidia Team
According to the Hardware Design Guide of the 10Gbit PHY AQR113C-B0-I, the crystal used should provide up to 350 uW drive strength. Now the one you use on the DevKit of the Orin AGX does “only” support ~200uW according to its datasheet:
Is this a mistake in the Design Guide of the PHY or why do you use the Crystal with lower drive strength?
Hi, DL of 8Z50002001 is 300uW in max. And can you share your guide doc of AQR113C-B0-I? I don’t see such data in its data sheet.
We cannot share the guide as it is confidential. The document name is “Hardware Design Guidelines AQR11x-AQR11xC Doc Rev-v4.00.pdf” if you want to request it from Marvell. In chapter “3.10.2 Crystal” it is written:
The clock crystal to be used with the PHY must have jitter tolerance of +/- 50 ppm or better and be capable
of driving up to 350 μW.
Got it, thanks. So far it works well. We are checking this internally, will update once available.
Hi, checked with vendor and get the feedback: 300uW will work fine. You will not have any issue in future. We recommend a higher value drive strength to keep a buffer.
This topic was automatically closed 14 days after the last reply. New replies are no longer allowed.