Are memory fetches 64 bytes _minimum_?

[Ailleur]

Hey all

Im doing some analysis for a paper im writing and ive stumbled upon a question ive never asked myself.

Assuming non coalesced memory reads (which is my case) are all memory fetches still AT LEAST 64 bytes (for compute capability 1.1)

As per the programming guide:

Second, global memory bandwidth is used most efficiently when the simultaneous

memory accesses by threads in a half-warp (during the execution of a single read or

write instruction) can be coalesced into a single memory transaction. The size of a

memory transaction can be either 32 bytes (for compute capability 1.2 and higher

only), 64 bytes, or 128 bytes.

So, im wondering.

Im trying to figure out if im bandwidth limited… Well, i know that i am, but im trying to put it in words.

If i use 64 bytes as the smallest possible memory transaction, i actually get a “higher than theoritical” bandwidth figure, which is of course wrong on my part.

So, does anyone know?

–edit

Well, now i see the memory bus (on my 8800gt) is 256 bits. So why would 32bytes reads not be supported on 1.1?

[paulius]

The minimum transaction is 32 bytes for 1.1.

The distinction is that 1.2 and higher could coalesce when 16 threads read bytes or shorts (16x1, or 16x2 byte transactions), whereas 1.1 could only coalesce when accessing 4, 8, or 16B words (breaking coalescing and issuing a separate transaction for each thread in other cases).

Paulius