I did a mistake in my design and used the pin-descriptions in the TX1-module data sheet (“Lane 0”, “Lane 1”, …) as indication for the PCIe-lane assignment instead of using the developer-kit data sheet as reference. After looking at the dev-kit data sheet it turns out that:
PCIe lane #0 <=> PEX0
PCIe lane #1 <=> SS1 (not PEX1)
PCIe lane #2 <=> PEX2
PCIe lane #3 <=> RFU (not SS1)
Because of this mismatch the link between my fpga-endpoint and the Tegra is established only with one lane instead of four.
My question is if it’s possible to reassign the lanes somehow by changing entries in the device tree-file, changing kernel driver-code or doing something else I’m not aware of (somehow control these pad control mux-things).
The figure 54 on page 1290 in the technical reference manual of the Tegra X1 gives me the impression that by somehow programming that mux-element you could freely route the lanes. But I’m not able to find any further information about this.
Thanks mrjazz2, the pins assignment in module datasheet is wrong, will be corrected in next version, please follow dev kit data sheet or OEM DG.