I am designing the AGX ORIN Carrier board and plan to design the USB I/F as shown below.
When configuring USB3.2 (HS&SS), there appears to be no specific mapping rule between HS and SS, but please confirm.
I am designing the AGX ORIN Carrier board and plan to design the USB I/F as shown below.
When configuring USB3.2 (HS&SS), there appears to be no specific mapping rule between HS and SS, but please confirm.
No specific mapping. Just you always need a USB2 lane along with your USB3 lane.
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