are there hash function in memory to cache mapping?

Hi nvidia,

We’d like to know about hash function between memory to cache mapping in TX1_Machine.

Our goal is to implement page coloring in TX1_Machine.

if there are hash function, it difficult to implement and want to know in advance.

and also, If a hash function exists, can I find the relevant documentation or information?


Hi hwPark,

We are checking internally with CPU HW team. Will revert soon.


Thank you for your reply.

we are sorry, but I have one more question.

we are trying to use u-boot bootloader to disable tx1_machine’s cache and memory prefetcher.

In this regard, I would like to know if there is a u-boot manual or example that allows us to access specific registers and change the relevant bit.


I am still waiting for your answer.

I am trying various ways to implement “page coloring” because I can not do anything while waiting for an answer. But it does not work well.

Your answer is more important because there is already a lot of time delay.

I would appreciate your reply.

Unfortunately, internals of ARM are not supposed to be disclosed. What is available online can be refer from here

What we want is not the way the “hash function” works, but the existence of it.

It will not be harmful to your security to simply identify the existence of a “hash function”.

I would appreciate it if you think about it again.