At TX1 Board, built-in TX1 CPU ISP working for Omnivision Camera Sensor ...

Dear NVidia SW Development Team …

nVidia TX1 CPU built-in ISP support related material … TX1 CPU’s built-in ISP says that it supports bypass mode
So, I understand that the NVIDIA Linux kernel supports SOC-type camera sensor operation.

So, DO ISP of the TX1 CPU Linux kernel support the RAW Camera mode of the OV5693.

That said, the built-in ISP of the TX1 CPU interprets that it supports OV5693’s Support Output Format: 10 bit RAW RGB, right?

So, in the above, the ISP of the TX1 CPU supports the RAW Camera mode of the OV5693 …

Does it mean that the ISP of the TX1 CPU converts the 10 bit RAW RGB image data of the OV5693 sensor output format to YUV422 data in the Linux kernel provided by nVidia?

Does NVIDIA support I2C table values for multiple camera sensors used by NVIDIA TX1 CPUs and the NVIDIA internal ISP’s tuned settings for I2C table values?

please answer about my question …

From
DMBTEC SW Devlopment Director
SeokWeon Jang

Bypass mode mean bypass ISP and get the RGB raw data from sensor to memory. For the bypass mode you need debayer the raw data to YUV or something else by software. The i2c table is not include any tuning table only the sensor initial table for the tuning you have to get help from scaling partner.

Does the TX1 CPU’s built-in ISP support the I2C settings table values required for operation when a new camera sensor is connected?

From
DMBTEC SW Devlopment Director
SeokWeon Jang

@sayhi7
I am not understand your question well. However the ISP and I2C setting is totally different things.

Is the camera sensor control of the internal ISP of the TX1 CPU controlled by I2C?

From
DMBTEC SW Devlopment Director
SeokWeon Jang

Not really ISP is build in tegra but sensor is 3rd party device control by i2c.

How much does a third-party vendor charge for controlling the internal ISP of the TX1 CPU with I2C?

From
DMBTEC SW Devlopment Director
SeokWeon Jang

What means Not really ISP is build in tegra ?

Is the built-in ISP control implemented in the Linux kernel of the TX1 CPU?

From
DMBTEC SW Devlopment Director
SeokWeon Jang

The ISP code is not public in kernel.

Can I get the built-in ISP source code of the TX1 CPU from a third party for a fee?

From
DMBTEC SW Devlopment Director
SeokWeon Jang

Sorry, we didn’t public this part.