We are designing a carrier board for Jetson Nano module. While designing we examined the module power on/off logic in “Jetson_Nano_Carrier_Board_Concept_Schematics.pdf” file. This file is available on the website of Nvidia. It is written that if latch_set and latch_set_but are not connected, auto-power-on is active. However, we could not understand the logic behind this circuit. There is a SR latch with NAND gates in this circuit. S and R inputs of the latch are both logic ‘1’ initially. This means outputs of NAND gates (named as power_en_q and power_en_q_bar in the document) should not change. How does power_en_q become logic ‘1’ initially? If it is related with pull-up resistor why does power_en_q_bar become logic ‘0’? Is there anyone who can clarify the logic behind this circuit?
Circuit is in the 13th page of pdf.
Jetson_Nano_Carrier_Board_Concept_Schematics.pdf (2.76 MB)