Auto-power-on topology for Jetson Nano Carrier Board

Autonomous Machines Jetson & Embedded Systems Jetson Nano
#1

Hi,
We are designing a carrier board for Jetson Nano module. While designing we examined the module power on/off logic in “Jetson_Nano_Carrier_Board_Concept_Schematics.pdf” file. This file is available on the website of Nvidia. It is written that if latch_set and latch_set_but are not connected, auto-power-on is active. However, we could not understand the logic behind this circuit. There is a SR latch with NAND gates in this circuit. S and R inputs of the latch are both logic ‘1’ initially. This means outputs of NAND gates (named as power_en_q and power_en_q_bar in the document) should not change. How does power_en_q become logic ‘1’ initially? If it is related with pull-up resistor why does power_en_q_bar become logic ‘0’? Is there anyone who can clarify the logic behind this circuit?

Circuit is in the 13th page of pdf.
Best Regards.
Jetson_Nano_Carrier_Board_Concept_Schematics.pdf (2.76 MB)

#2

Hi, there is timing difference between latch_set and latch_reset going high as there is a 470k pull-up and 47nF cap on latch_set which will cause latch_set rising later than latch_reset.

#3

@Trumany thanks for your reply. I got the point.

#4

How does jumper between latch_set_but and latch_set disable auto power on?

#5

It’s J41 in current docs released, you can set it to short to disable auto power on.

#6

Hi again,
Firstly, thanks for your reply. However, I could not understand how auto power on is disabled after connecting latch_set_but and latch_set. By considering your first answer, I realized that using cap and pull up resistor helps us to enable auto power on without connecting latch_set and latch_set_but. While we do not connect latch_set_but and latch_set, there is an RC circuit on the latch set side. Time constant for this circuit is almost 22 ms and this is enough to start auto power on. On the other hand, after connecting latch_set_but and latch_set, there is an also RC circuit. In this circuit, time constant decreased drastically (It is almost 5.17 us). I guess this is enough to enable power automatically. I am not sure whether I could not get any point.
Thanks in advance.

#7

The real power on signal to module is POWER_EN, it have at least 30ms Debounce Time as de-twitter.
By your calc 5.17 us not long enough as valid power on.
Make sense to you?

#8

Hi,
Thanks for your reply.

Case 1: J40 jumper is not connected

R*C = 22 ms

Case 2 : J40 jumper is connected

R*C = 5.17 us (due to 110 ohm resistor)

What do you mean by 30 ms debounce time? Why is 30 ms debounce time necessary?

#9

30ms Debounce Time is POWER_EN spec.
It means a valid power on need H logic > 30ms time on POWER_EN.

#10

How do you reach this spec? I could not find this in any released documents for Jetson Nano.

#11

Yes not infinite details listed in public document.
Follow https://developer.nvidia.com/embedded/dlc/jetson-nano-product-design-guide do carrier design.
This forum have Nvidia support team work on can provide the missing info.

#12

I folowed design guide for jetson nano and also examined on different documents that were released by Nvidia. However, this topic is not clear.

#13

Even if J40 jumper is connected, is 5.17 us enough time to make power_en_q signal logic high? After capacitor is fully charged (within 10-25 us), both of latch set and latch reset become 1 and there is no change in the power_en_q signal. It means power_en will be logic high more than 30 ms. Am i wrong?

#14

If J40 jumper is connected, LATCH_SET charge faster than LATCH_RESET, that will make POWER_EN_Q to “set”/logic L before to “no change”.
If you have Nano devkit on hand do some probe by oscilloscope will help you understand, this circuit work.

#15

There is no capacitor in latch reset leg. How does latch_set charge faster than latch_reset? I have no available Nano devkit now.

#16

C278 stuff 1uF on production devkit.
Why are you keep asking this, are you doing design of your own carrier board? Better get a real work Devkit do some test to make sure everything work as expectation。

#17

Yeah we design a carrier board by using the same topology

#18

C278 capacitor is seemed as “no stuff” in the document that i attached this post. However, you said that c278 stuff. Is there a fault in the document?

#19

Hi,
It’s not document error just have updated version, the newer version will be in download center in later time.

#20

Hi,
Is there any other updates in this circuit? (Including stuff and no stuff circuit elements)