Auvidea J120 with TX2 & Jetpack 4.2

Robotics & Edge Computing Jetson & Embedded Systems Jetson TX2
1

I sent this to Auvidea support but haven’t heard anything back, so I figured I’d ask here.

Short version - I patched the 4.2 DTS files based off the sources provided by Auvidea for 3.2 (did a 3.2 stock vs the files from the auvidea patch). Everything on the J120 seems good except for the bottom USB port, which is totally unresponsive. Wondering if anyone has any ideas on how to debug that.

More detail - the most recent auvidea release is for Jetpack 3.2, and includes modified dts files. I ran a diff of those against the default dts files provided in the Jetpack 3.2 kernel source. Using that diff, I patched the 4.2 dts files, built, then flashed them using the normal process for 4.2.

The top full-size USB, side micro USB, fan, and so on all seem to work normally. The bottom USB port doesn’t seem to respond to anything.

Here’s a diff of my 4.2 hardware vs. stock :

diff -cbwr hardware.orig/nvidia/platform/t18x/common/kernel-dts/t18x-common-platforms/tegra186-quill-power-tree-p3310-1000-a00-00.dtsi hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-platforms/tegra186-quill-power-tree-p3310-1000-a00-00.dtsi
*** hardware.orig/nvidia/platform/t18x/common/kernel-dts/t18x-common-platforms/tegra186-quill-power-tree-p3310-1000-a00-00.dtsi	2019-03-11 02:29:04.000000000 -0400
--- hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-platforms/tegra186-quill-power-tree-p3310-1000-a00-00.dtsi	2019-05-03 22:58:36.741529566 -0400
***************
*** 120,132 ****
  		avdd_pll_erefeut-supply = <&spmic_sd2>;
  	};
  
- 	spi@c260000 {
- 		spi-touch-sharp19x12@0 {
- 			avdd-supply = <&en_vdd_ts_hv_3v3>;
- 			dvdd-supply = <&en_vdd_ts_1v8>;
- 		};
- 	};
- 
  	pcie-controller@10003000 {
  		dvdd-pex-supply = <&spmic_ldo7>;
  		hvdd-pex-pll-supply = <&spmic_sd2>;
--- 120,125 ----
diff -cbwr hardware.orig/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3310-1000-a00-00-base.dts hardware/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3310-1000-a00-00-base.dts
*** hardware.orig/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3310-1000-a00-00-base.dts	2019-03-11 02:29:12.000000000 -0400
--- hardware/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3310-1000-a00-00-base.dts	2019-05-05 15:37:04.573524998 -0400
***************
*** 128,134 ****
  		status = "okay";
  		phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
  			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(1)>,
! 			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(1)>;
  		phy-names = "utmi-0", "utmi-1", "usb3-1";
  		nvidia,boost_cpu_freq = <800>;
  	};
--- 128,134 ----
  		status = "okay";
  		phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
  			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(1)>,
! 			<&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(0)>;
  		phy-names = "utmi-0", "utmi-1", "usb3-1";
  		nvidia,boost_cpu_freq = <800>;
  	};
***************
*** 222,238 ****
--- 222,241 ----
  				nvidia,function = "xusb";
  				nvidia,port-cap = <TEGRA_PADCTL_PORT_OTG_CAP>;
  				nvidia,oc-pin = <0>;
+ 				status = "okay";
  			};
  			usb2-std-A-port2 {
  				nvidia,lanes = "otg-1";
  				nvidia,function = "xusb";
  				nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
  				nvidia,oc-pin = <1>;
+ 				status = "okay";
  			};
  			usb3-std-A-port2 {
  				nvidia,lanes = "usb3-1";
  				nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
  				nvidia,oc-pin = <1>;
+ 				status = "okay";
  			};
  
  			e3325-usb3-std-A-HS {
***************
*** 284,292 ****
--- 287,323 ----
  			status = "disabled";
  			dp-display {
  				status = "disabled";
+  				nvidia,fbcon-default-mode {
+  					clock-frequency = <27027000>;
+  					hactive = <720>;
+  					vactive = <480>;
+  					hfront-porch = <16>;
+  					hback-porch = <60>;
+  					hsync-len = <62>;
+  					vfront-porch = <9>;
+  					vback-porch = <30>;
+  					vsync-len = <6>;
+  					nvidia,h-ref-to-sync = <1>;
+  					nvidia,v-ref-to-sync = <1>;
+  					vmode = <0x400000>;	/* FB_VMODE_NONINTERLACED | FB_VMODE_IS_CEA */
+  				};
  			};
  			hdmi-display {
  				status = "disabled";
+  				nvidia,fbcon-default-mode {
+  					clock-frequency = <27027000>;
+  					hactive = <720>;
+  					vactive = <480>;
+  					hfront-porch = <16>;
+  					hback-porch = <60>;
+  					hsync-len = <62>;
+  					vfront-porch = <9>;
+  					vback-porch = <30>;
+  					vsync-len = <6>;
+  					nvidia,h-ref-to-sync = <1>;
+  					nvidia,v-ref-to-sync = <1>;
+  					vmode = <0x400000>;	/* FB_VMODE_NONINTERLACED | FB_VMODE_IS_CEA */
+  				};
  			};
  
  			panel-s-edp-uhdtv-15-6 {
***************
*** 305,313 ****
--- 336,373 ----
  			nvidia,active-panel = <&sor1_hdmi_display>;
  			hdmi-display {
  				status = "okay";
+  				/*nvidia,fbcon-default-mode {
+  					clock-frequency = <27027000>;
+  					hactive = <720>;
+  					vactive = <480>;
+  					hfront-porch = <16>;
+  					hback-porch = <60>;
+  					hsync-len = <62>;
+  					vfront-porch = <9>;
+  					vback-porch = <30>;
+  					vsync-len = <6>;
+  					nvidia,h-ref-to-sync = <1>;
+  					nvidia,v-ref-to-sync = <1>;
+  					vmode = <0x400000>;	// FB_VMODE_NONINTERLACED | FB_VMODE_IS_CEA
+  				};*/
  			};
  			dp-display {
  				status = "disabled";
+  				nvidia,fbcon-default-mode {
+  					clock-frequency = <27027000>;
+  					hactive = <720>;
+  					vactive = <480>;
+  					hfront-porch = <16>;
+  					hback-porch = <60>;
+  					hsync-len = <62>;
+  					vfront-porch = <9>;
+  					vback-porch = <30>;
+  					vsync-len = <6>;
+  					nvidia,h-ref-to-sync = <1>;
+  					nvidia,v-ref-to-sync = <1>;
+  					vmode = <0x400000>;	/* FB_VMODE_NONINTERLACED | FB_VMODE_IS_CEA */
+  				};
+ 
  			};
  		};
  
diff -cbwr hardware.orig/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3310-1000-c03-00-base.dts hardware/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3310-1000-c03-00-base.dts
*** hardware.orig/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3310-1000-c03-00-base.dts	2019-03-11 02:29:12.000000000 -0400
--- hardware/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3310-1000-c03-00-base.dts	2019-05-03 22:57:10.491159846 -0400
***************
*** 185,188 ****
--- 185,279 ----
  			};
  		};
  	};
+  
+  	//SPI1                     0x03210000    0x0321ffff        arspi.h
+  	//SPI2    AON_CLUSTER        0x0c260000    0x0c26ffff        arspi.h
+  	//SPI3                     0x03230000    0x0323ffff        arspi.h
+  	//SPI4                     0x03240000    0x0324ffff        arspi.h
+  
+  	//3240000 
+  	//c260000
+  
+  	//SPI0 E3 F3 E4 F4 G14=Interrupt SPI0 before "Display Connector" now "IMU"
+  	spi@c260000 {
+  		status = "okay";
+  		spidev@0 {
+  			#address-cells = <0x1>;
+  			#size-cells = <0x0>;
+  			compatible = "spidev";
+  			reg = <0>;
+  			spi-max-frequency=<25000000>;
+  			irq-gpio = <&tegra_aon_gpio TEGRA_AON_GPIO(AA, 2) 0x01>;
+  			interrupt-parent = <&tegra_aon_gpio>;
+  			interrupts = <TEGRA_AON_GPIO(AA, 2) 0x01>; /* GPIO_PAA2 */
+  		};
+  	};
+  
+  
+  	//SPI1 G13 E14 F14 F13 before Expansion Header now CAN-MCP251x
+  	spi@3240000 {
+  		status = "okay";
+  		spidev@0 {
+  			compatible = "spidev";
+  			reg = <0>;
+  			spi-max-frequency=<25000000>;
+  		};
+  		spidev@1 {
+  			compatible = "spidev";
+  			reg = <1>;
+  			spi-max-frequency=<25000000>;
+  		};
+  
+  	};
+  
+  	//SPI2 H14 H15 G15 G16 F16 before Expansion Header now SPI connector
+  	spi@3230000 {
+  		status = "okay";
+  		spidev@0 {
+  			compatible = "spidev";
+  			reg = <0>;
+  			spi-max-frequency=<25000000>;
+  		};
+  		spidev@1 {
+  			compatible = "spidev";
+  			reg = <1>;
+  			spi-max-frequency=<25000000>;
+  		};
+  	};
+  
+  
+  	fixed-regulators {
+  		vdd_fan: regulator@13 {
+  			gpio = <&tegra_main_gpio TEGRA_MAIN_GPIO(J, 6) GPIO_ACTIVE_LOW>;  //alternative gpio for auvidea carrier boards
+  		};
+  	};
+  
+  	pwm_fan_shared_data: pfsd {
+  		status = "okay";
+  		num_resources = <0>;
+  		secret = <47>;
+  		active_steps = <10>;
+  		active_rpm = <0 1000 2000 3000 4000 5000 6000 7000 10000 11000>;
+  		rpm_diff_tolerance = <2>;
+  		active_rru = <40 2 1 1 1 1 1 1 1 1>;
+  		active_rrd = <40 2 1 1 1 1 1 1 1 1>;
+  		state_cap_lookup = <2 2 2 2 3 3 3 4 4 4>;
+  		pwm_period = <45334>;
+  		pwm_id = <4>;
+  		step_time = <100>; /* mesecs */
+  		state_cap = <7>;
+  		active_pwm_max = <256>;
+  		tach_period = <1000>;
+  		//pwm_gpio = <&tegra_aon_gpio TEGRA_AON_GPIO(V, 6) GPIO_ACTIVE_LOW>; /* TEGRA_MAIN_GPIO_PV6 */
+  		//pwm_gpio = <&tegra_main_gpio TEGRA_MAIN_GPIO(J, 6) GPIO_ACTIVE_LOW>; /* TEGRA_MAIN_GPIO_PJ6 */
+  	};
+  	pwm-fan {
+  		status = "okay";
+  		compatible = "pwm-fan";
+  
+  		shared_data = <&pwm_fan_shared_data>;
+  		active_pwm = <0 80 120 160 255 255 255 255 255 255>;
+  	};
+  
+ 
  };

I’m guessing that there’s something new in the 4.2 dts files that needs to be tweaked, but I’m mostly flying blind - copy and pasting rather than understanding. Any ideas would be appreciated

2

hi, i have the same problem ,so email j120 too and got this reply :

"There is, unfortunately, no way to use the second USB port. It is not because of the drivers, it’s because, in the hardware, the port can’t be physically connected to the TX2 module.

There is no need to install any additional drivers, just install through the SDK manager the Jetpack 4.2 image and the module should work without any problems (except second USB port)."

but about the fan,I just exchange the Auvidea3.2 , seems not work , when I run ,the fan will run second ,then stop, if its auto like in jetpack 3.3?

3

That’s weird, I was sure the bottom USB port worked previously.

For the fan, my definition of “working” was that it ran after running jetson_clocks. That’s our normal operating procedure anyway (nvpmodel -m 0 followed by jetston_clocks) so I didn’t look at behavior in other situations.

4

The J120 supports 2 USB 3.0 ports with the TX1. Due to pin muxing limitations of the TX2 it only can support 1 USB 3.0 port (the upper one). The lower port will just be USB 2.0. To enable these USB ports device tree changes are required.

We are now introducing the J120 rev 9 which will not necessarily need the device tree changes. It will work with the standard dev kit image.

J121 with 2 USB 3.0 ports
Also we are introducing the J121 which will fully support the TX2. So it supports 2 USB 3.0 ports. To enable this the config 6 (for pin muxing) must be selected in the device tree. The J121 is mechanically compatible to the J120. So it can use the same enclosures.

5

I also try to running jetson_clocks. But it’s said can not access fun。 Do you know what’s happened about this？ By the way, I run it in terminal ， Because I can’t run it by double_click， And also I can’t run anything by double_click， Even its executable file， In jetpack 3.3， This case never happend！

6

I mean I just terminal in user/bin and type sudo ./jetson_clocks.it says can not access fan,even the modle is 0, The fan is still doesnt work.

7

Do you see the target_pwm special file (this is the default location for R32.1, and probably most others, but you can verify by finding the file name with “grep fan which jetson_clocks”)?

sudo ls -l /sys/devices/pwm-fan/target_pwm

If that file does not exist, then a kernel driver is not running and could explain a lack of permission from “sudo jetson_clocks”. If the file is missing, then perhaps device tree is the cause since it is a different carrier board from the dev kit.

8

[b]

We are now introducing the J120 rev 9 which will not necessarily need the device tree changes. It will work with the standard dev kit image.

[/b]

Is there an updated j90 board rev that is compatible with the standard tx2 dev kit image?

9

I couldn’t tell you how the j90 is set up. If it is an exact match to the dev kit in terms of which module pin goes to what carrier detail, then the device tree would probably be a match for the standard dev kit. For the purposes of this particular thread, the file “/sys/devices/pwm-fan/target_pwm” should exist and allow changing fan speed modes if this is the case.

10

If I want to replace the kernel drives, where do I need to find out in sdk download？
I found the following two files path：

  1. /home/tulagu/nvidia/nvidia_sdk/JetPack_4.2_Linux_P3310/Linux_for_Tegra/kernel/dtb/

  2. /home/tulagu/Downloads/nvidia/sdkm_downloads/Jetson_Linux_R32.1.0_aarch64.tbz2/Linux_for_Tegra/kernel/dtb/

which is the kernel in ? or the dtb in ?

11

Do you actually mean that you want to change the drivers (such as adding more or editing something which is already in place)? If so, this is mostly just building new modules or a kernel and file copies. Device tree is used by the drivers, but is more or less independent in how this is updated or edited.

Any driver is part of the kernel, and has assorted parameters. The driver tends to be somewhat generic, but needs details of the particular hardware installation (for example one manufacturer might route a controller to a different pin than does the other manufacturer). The device tree is a method of naming the parameters specific to a given board design. One would change the device tree to deal with different layouts of the same driver of the same chipset. Thus the device tree and driver work together, but in terms of changing a driver everything is done with kernel build (and modules are part of kernel build even in the module format).

The kernel is in “/boot”. The modules are in “/lib/modules/$(uname -r)/”. The device tree is in a partition (and is signed binary data). Other than typically cross compiling kernels/modules this isn’t much different from a desktop PC (and I tend to natively compile on the Jetson anyway). The actual device tree tools are the same across most any Linux platform, but the actual install steps differ. Details on what you would like to accomplish would make it easier to answer (or at least to give a meaningful answer).

12

Hi, could you pls publish the changes needed to enable the J120 Rev 8 board with the Jetpack 4.2 version on TX2?
I need one USB3.0 port with my current project, the second USB is not needed as long as at least the micro USB port is working in parallel to the USB3.0 port. Thanks!

13

@mtbsteve: Changes for a J120 Rev 8 would have to come from the manufacturer. Typically this would be a device tree edit, but I could not give details of any particular custom carrier. There is usually a lag between when a new L4T release is out and when a custom carrier manufacturer posts the board support package for the new release (the BSP would consist mostly of a device tree edit).

14

@linuxdev thanks but I was asking for the necessary changes to use the J120 USB ports alongside with Jetpack 4.2.

The J120 firmware and drivers on the Auvidea support site are still referring to Jetpack 3.2.
Has anyone successfully running the TX2 on a J120 board with Jetpack 4.2 installed and can let me know please what’s required to support USB3.0 and a USB 2.0 port?

1 Like
15

Depending on the rev of your J120 board, in order to support one usb3.0 and one usb2.0 you will need to apply the appropriate device tree changes noted above in the previous comments of this thread. If you have a J120 rev 9 board, it should already be compatible with the latest Jetpack 4.2 dev kit image.

16

Auvidea released firmware support for Jetpack 4.2 for their Jetson TX2 carrier boards. Does anyone tested it with the carrier J90x?

Thank you.

17

Hi,

I have tested Jetpack 4.2 for J120 with TX2 and it is working correctly, I tested: USB port, ethernet port and HDMI port. Please see more details here:

[url]https://devtalk.nvidia.com/default/topic/1055499/jetson-tx2/tx2-amp-auvidea-j120-setup-jetpack4-2/post/5351299/#5351299[/url]

18

Thanks @ManuelLeiva.
Does that mean that the Auvidea Firmware 2.0 instructions (see Firmware – Auvidea) for the J120 with JP4.2 are not working?

19

Mtbsteve,

I have not tried Auvidea Firmware 2.0 instructions (How_to_install_kernel_with_nvidia_sdk.txt) therefore I don’t know if these instructions are working. These instructions provide the steps to load pre-built images.

I am using J120 with JP4.2 using the kernel sources provided by Auvidea (J120_4.2/kernel_src)

You can use these instruction to compile the kernel sources if you want to try this approach:

20

@admin9or24: I have a J120 (purchased a few weeks ago from Mouser) with a TX2 mounted on it. I’ve followed the directions to install the May 2019 firmware release from Auvidea (https://www.auvidea.eu/download/firmware/TX2/v2.0/J120_4.2.zip).

After this setup process, no SPI ports appear to be supported. That is, the spidev driver is never loaded. @ManuelLeiva, did you by any chance notice if your SPI port was working after you did the procedure you describe above?

@admin9or24, does Auvidea have a firmware patch that supports the SPI ports on the J120?