I sent this to Auvidea support but haven’t heard anything back, so I figured I’d ask here.
Short version - I patched the 4.2 DTS files based off the sources provided by Auvidea for 3.2 (did a 3.2 stock vs the files from the auvidea patch). Everything on the J120 seems good except for the bottom USB port, which is totally unresponsive. Wondering if anyone has any ideas on how to debug that.
More detail - the most recent auvidea release is for Jetpack 3.2, and includes modified dts files. I ran a diff of those against the default dts files provided in the Jetpack 3.2 kernel source. Using that diff, I patched the 4.2 dts files, built, then flashed them using the normal process for 4.2.
The top full-size USB, side micro USB, fan, and so on all seem to work normally. The bottom USB port doesn’t seem to respond to anything.
Here’s a diff of my 4.2 hardware vs. stock :
diff -cbwr hardware.orig/nvidia/platform/t18x/common/kernel-dts/t18x-common-platforms/tegra186-quill-power-tree-p3310-1000-a00-00.dtsi hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-platforms/tegra186-quill-power-tree-p3310-1000-a00-00.dtsi
*** hardware.orig/nvidia/platform/t18x/common/kernel-dts/t18x-common-platforms/tegra186-quill-power-tree-p3310-1000-a00-00.dtsi 2019-03-11 02:29:04.000000000 -0400
--- hardware/nvidia/platform/t18x/common/kernel-dts/t18x-common-platforms/tegra186-quill-power-tree-p3310-1000-a00-00.dtsi 2019-05-03 22:58:36.741529566 -0400
***************
*** 120,132 ****
avdd_pll_erefeut-supply = <&spmic_sd2>;
};
- spi@c260000 {
- spi-touch-sharp19x12@0 {
- avdd-supply = <&en_vdd_ts_hv_3v3>;
- dvdd-supply = <&en_vdd_ts_1v8>;
- };
- };
-
pcie-controller@10003000 {
dvdd-pex-supply = <&spmic_ldo7>;
hvdd-pex-pll-supply = <&spmic_sd2>;
--- 120,125 ----
diff -cbwr hardware.orig/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3310-1000-a00-00-base.dts hardware/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3310-1000-a00-00-base.dts
*** hardware.orig/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3310-1000-a00-00-base.dts 2019-03-11 02:29:12.000000000 -0400
--- hardware/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3310-1000-a00-00-base.dts 2019-05-05 15:37:04.573524998 -0400
***************
*** 128,134 ****
status = "okay";
phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(1)>,
! <&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(1)>;
phy-names = "utmi-0", "utmi-1", "usb3-1";
nvidia,boost_cpu_freq = <800>;
};
--- 128,134 ----
status = "okay";
phys = <&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(0)>,
<&tegra_xusb_padctl TEGRA_PADCTL_PHY_UTMI_P(1)>,
! <&tegra_xusb_padctl TEGRA_PADCTL_PHY_USB3_P(0)>;
phy-names = "utmi-0", "utmi-1", "usb3-1";
nvidia,boost_cpu_freq = <800>;
};
***************
*** 222,238 ****
--- 222,241 ----
nvidia,function = "xusb";
nvidia,port-cap = <TEGRA_PADCTL_PORT_OTG_CAP>;
nvidia,oc-pin = <0>;
+ status = "okay";
};
usb2-std-A-port2 {
nvidia,lanes = "otg-1";
nvidia,function = "xusb";
nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
nvidia,oc-pin = <1>;
+ status = "okay";
};
usb3-std-A-port2 {
nvidia,lanes = "usb3-1";
nvidia,port-cap = <TEGRA_PADCTL_PORT_HOST_ONLY>;
nvidia,oc-pin = <1>;
+ status = "okay";
};
e3325-usb3-std-A-HS {
***************
*** 284,292 ****
--- 287,323 ----
status = "disabled";
dp-display {
status = "disabled";
+ nvidia,fbcon-default-mode {
+ clock-frequency = <27027000>;
+ hactive = <720>;
+ vactive = <480>;
+ hfront-porch = <16>;
+ hback-porch = <60>;
+ hsync-len = <62>;
+ vfront-porch = <9>;
+ vback-porch = <30>;
+ vsync-len = <6>;
+ nvidia,h-ref-to-sync = <1>;
+ nvidia,v-ref-to-sync = <1>;
+ vmode = <0x400000>; /* FB_VMODE_NONINTERLACED | FB_VMODE_IS_CEA */
+ };
};
hdmi-display {
status = "disabled";
+ nvidia,fbcon-default-mode {
+ clock-frequency = <27027000>;
+ hactive = <720>;
+ vactive = <480>;
+ hfront-porch = <16>;
+ hback-porch = <60>;
+ hsync-len = <62>;
+ vfront-porch = <9>;
+ vback-porch = <30>;
+ vsync-len = <6>;
+ nvidia,h-ref-to-sync = <1>;
+ nvidia,v-ref-to-sync = <1>;
+ vmode = <0x400000>; /* FB_VMODE_NONINTERLACED | FB_VMODE_IS_CEA */
+ };
};
panel-s-edp-uhdtv-15-6 {
***************
*** 305,313 ****
--- 336,373 ----
nvidia,active-panel = <&sor1_hdmi_display>;
hdmi-display {
status = "okay";
+ /*nvidia,fbcon-default-mode {
+ clock-frequency = <27027000>;
+ hactive = <720>;
+ vactive = <480>;
+ hfront-porch = <16>;
+ hback-porch = <60>;
+ hsync-len = <62>;
+ vfront-porch = <9>;
+ vback-porch = <30>;
+ vsync-len = <6>;
+ nvidia,h-ref-to-sync = <1>;
+ nvidia,v-ref-to-sync = <1>;
+ vmode = <0x400000>; // FB_VMODE_NONINTERLACED | FB_VMODE_IS_CEA
+ };*/
};
dp-display {
status = "disabled";
+ nvidia,fbcon-default-mode {
+ clock-frequency = <27027000>;
+ hactive = <720>;
+ vactive = <480>;
+ hfront-porch = <16>;
+ hback-porch = <60>;
+ hsync-len = <62>;
+ vfront-porch = <9>;
+ vback-porch = <30>;
+ vsync-len = <6>;
+ nvidia,h-ref-to-sync = <1>;
+ nvidia,v-ref-to-sync = <1>;
+ vmode = <0x400000>; /* FB_VMODE_NONINTERLACED | FB_VMODE_IS_CEA */
+ };
+
};
};
diff -cbwr hardware.orig/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3310-1000-c03-00-base.dts hardware/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3310-1000-c03-00-base.dts
*** hardware.orig/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3310-1000-c03-00-base.dts 2019-03-11 02:29:12.000000000 -0400
--- hardware/nvidia/platform/t18x/quill/kernel-dts/tegra186-quill-p3310-1000-c03-00-base.dts 2019-05-03 22:57:10.491159846 -0400
***************
*** 185,188 ****
--- 185,279 ----
};
};
};
+
+ //SPI1 0x03210000 0x0321ffff arspi.h
+ //SPI2 AON_CLUSTER 0x0c260000 0x0c26ffff arspi.h
+ //SPI3 0x03230000 0x0323ffff arspi.h
+ //SPI4 0x03240000 0x0324ffff arspi.h
+
+ //3240000
+ //c260000
+
+ //SPI0 E3 F3 E4 F4 G14=Interrupt SPI0 before "Display Connector" now "IMU"
+ spi@c260000 {
+ status = "okay";
+ spidev@0 {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ compatible = "spidev";
+ reg = <0>;
+ spi-max-frequency=<25000000>;
+ irq-gpio = <&tegra_aon_gpio TEGRA_AON_GPIO(AA, 2) 0x01>;
+ interrupt-parent = <&tegra_aon_gpio>;
+ interrupts = <TEGRA_AON_GPIO(AA, 2) 0x01>; /* GPIO_PAA2 */
+ };
+ };
+
+
+ //SPI1 G13 E14 F14 F13 before Expansion Header now CAN-MCP251x
+ spi@3240000 {
+ status = "okay";
+ spidev@0 {
+ compatible = "spidev";
+ reg = <0>;
+ spi-max-frequency=<25000000>;
+ };
+ spidev@1 {
+ compatible = "spidev";
+ reg = <1>;
+ spi-max-frequency=<25000000>;
+ };
+
+ };
+
+ //SPI2 H14 H15 G15 G16 F16 before Expansion Header now SPI connector
+ spi@3230000 {
+ status = "okay";
+ spidev@0 {
+ compatible = "spidev";
+ reg = <0>;
+ spi-max-frequency=<25000000>;
+ };
+ spidev@1 {
+ compatible = "spidev";
+ reg = <1>;
+ spi-max-frequency=<25000000>;
+ };
+ };
+
+
+ fixed-regulators {
+ vdd_fan: regulator@13 {
+ gpio = <&tegra_main_gpio TEGRA_MAIN_GPIO(J, 6) GPIO_ACTIVE_LOW>; //alternative gpio for auvidea carrier boards
+ };
+ };
+
+ pwm_fan_shared_data: pfsd {
+ status = "okay";
+ num_resources = <0>;
+ secret = <47>;
+ active_steps = <10>;
+ active_rpm = <0 1000 2000 3000 4000 5000 6000 7000 10000 11000>;
+ rpm_diff_tolerance = <2>;
+ active_rru = <40 2 1 1 1 1 1 1 1 1>;
+ active_rrd = <40 2 1 1 1 1 1 1 1 1>;
+ state_cap_lookup = <2 2 2 2 3 3 3 4 4 4>;
+ pwm_period = <45334>;
+ pwm_id = <4>;
+ step_time = <100>; /* mesecs */
+ state_cap = <7>;
+ active_pwm_max = <256>;
+ tach_period = <1000>;
+ //pwm_gpio = <&tegra_aon_gpio TEGRA_AON_GPIO(V, 6) GPIO_ACTIVE_LOW>; /* TEGRA_MAIN_GPIO_PV6 */
+ //pwm_gpio = <&tegra_main_gpio TEGRA_MAIN_GPIO(J, 6) GPIO_ACTIVE_LOW>; /* TEGRA_MAIN_GPIO_PJ6 */
+ };
+ pwm-fan {
+ status = "okay";
+ compatible = "pwm-fan";
+
+ shared_data = <&pwm_fan_shared_data>;
+ active_pwm = <0 80 120 160 255 255 255 255 255 255>;
+ };
+
+
};
I’m guessing that there’s something new in the 4.2 dts files that needs to be tweaked, but I’m mostly flying blind - copy and pasting rather than understanding. Any ideas would be appreciated