Available GPIO pins on TX1 J21 header

How many GPIO pins are available for the user on J21 header of TX1 board? After searching through the documents, I have found out that out of total of 40 pins on this header, most of them are reserved for 5V, 3.3V, GND, I2C and Serial signals. The remaining ones also have some kind of signal type associated with them. So how many GPIO pins are left after that?
Could someone please help me with this ASAP?


You may read this page.

I have already gone through that article. It says that there are just 8 pins available for the user but I am not satisfied with that. How about the pins 7,11,12,15 which are not reserved for 5V, 3.3V, GND or I2C, but this article does not specify that these pins can be used for other purposes.

Also there is another GPIO expansion header on TX1, J26. How many unused pins do we have on it?

Could someone please provide a better explanation?

There is a similar listing on that same server (the TX1 and TX2 dev kits use the same carrier):

There is a similar diagram for the TX1: https://www.jetsonhacks.com/nvidia-jetson-tx1-j21-header-pinout/

It is not clear what the term “I am not satisfied by the answer” might mean. The headers are configurable, depending on how the pinmux is mapped on the Tegra chip. If you are not satisfied by the answer and need a more thorough understanding of how this works, please refer to the TRM, the pinmux sheet and the kernel source code.

The term “reserved” referenced means that NVIDIA strongly advises that if you implement that function, you should use the pins set aside for the function as specified. If you do not use that function, it is free to use as you would like. You should note that if you use those pins however, their function may change in future software releases.

Thank you so much Kangalow!!
You answered my question completely.