I am using Jetson Orin Nano kit with Jetpack 6.2 Tegra234. Using Jetosn-io I have enabled the I2S2 interface and have set the clock rate to 1.536MHz in the device tree ../hardware/nvidia/t23x/nv-public/tegra234/dtsi.
I have noticed upon boots, the clock rate is at 1.41MHz and sampling rate is at 44KHz. looking at /sys/…clk/clk_tree, I see that I2S2 is set to that rate.
after I run amixer and aplay, the bit clock changes and I read a correct clock frequency that is set by the sample rate and number of channels and number of bits per sample from the .wav input(regardless of what clock rate has been set in the device tree or what’s noted in clk_tree).
I would like to know where I can control the bit clock and sample clock upon boots, so really asking where I can change the 1.41MHz and 44KHz to 3.072MHz and 48KHz after boot and how to run it continuously so I don’t have to run amixer/aplay. Basically, which device overlay to modify to change the bit-clock and fs clock rates?
Hi Yasmin,
Though, we set rates with DT, it can be changed based on usecase sampling rate played after boot. I suspect boot sound getting played at 44.1KHz which is changing the I2S rate during ubuntu gui bootup.
Can you try with below change
vim /etc/pulse/daemon.conf
Just look for the line
;default-sample-rate = 44100
Change the above line as
default-sample-rate = 48000
Reboot the system.
If you are looking for 48KHz signals from I2S after boot continuously, without running aplay/arecord SW doesn’t enable I2S by default. Will it be fine to config amixer and aplay during boot to run the 48KHz audio by default?.
Additionally, the Jetson Orin Nano’s I²S interface (configured as a bit clock master by default) automatically adjusts the bit clock based on the audio playback or capture use case.
To achieve a 3.072 MHz bit clock, you could try playing a 48 kHz, 2-channel, 32-bit WAV file using aplay. You might consider adding this to the .bashrc or system initialization script to keep it running and maintain the clock.
By the way, are you planning to use the I2S2 FSYNC as a reference for your A2B bus setup?
changing the clock rate in /etc/pulse/daemon.conf did not help. Adding the amixer/aplay commands to the bashrc works but that requires a terminal to open. I ended up creating systemd service unit to get continuous clocks at boot. Basically created a bash file that includes the amixer/aplay audio settings (in a loop) in /usr/local/bin/myscript.bash and created a systemd unit service here: /etc/systemd/system/myscript.service. I have continuous clock at boot now.
In DT nv-public/nv-soc/tegra234-soc-audio-dai-links.dtsi what do I need to change to make sure the I2S TDM configuration matches between the Jetson (as specified in the device tree) and the my A2B nodes?
Device Tree (DT) is one way to modify the Jetson I2S properties for the DAI link. In addition, mixer controls are available for configuring I2S settings at runtime instead of DT.
For example, as documented here, you can refer the highlighted I2S configuration mixer control commands:
$ amixer -c APE cset name="I2S4 codec master mode" "cbs-cfs"
$ amixer -c APE cset name="I2S4 codec frame mode" "dsp-b"
$ amixer -c APE cset name="I2S4 FSYNC Width" 0
For a better understanding of frame mode, master mode, and FSYNC width, please refer to the link above as well as the section here.
To give a quick summary:
FSYNC Width = 0 means the frame sync signal stays high for 1 bit period. A value of 31 means it stays high for 32 bit periods.
DSP-A and DSP-B are TDM modes: DSP-B starts data in sync with FSYNC, while DSP-A introduces a 1-bit delay after FSYNC.
Codec master mode “cbs-cfs” implies the Jetson I2S is acting as the bit clock (BCLK) and frame sync (FSYNC) master.
Please verify the Jetson I2S configuration and ensure it aligns correctly with your A2B TDM setup. If it does not allign you may have to change I2S configuration via mixer controls as suitable
The entire communication issue was related to the quality of clocks from Jetson. Once I provided clocks from the master board(EVAL-AD2433WA1BZ), the nodes were discovered and stayed powered up(the quality of Fs clock is important for A2B PLL to lock). I guess Jetson does not provide clean clocks. See the plot below(too much ringing).
I don’t measure 50% duty cycle on FS clock straight from Jetson I2S0_FS(pin 35) . Please advise what I need to change in DT or amixer settings to achieve this?
Your observation aligns with the expected behavior. By default, the fsync-width is set to 1 bit, which results in a shorter fsync pulse. When you changed the value to 31, corresponding to a 32-bit wide fsync pulse, you observed a wider fsync pulse. fsync-width configuration is decided based on peripheral /codec attached. Hence default value of 1 is chosen and a provision is given for customisation.
For your test, either you could add below command (as I see that you are playing 32 bit stereo file, one frame cycle is 64 bits and 50% duty cycle is 32 bits)
Thanks, that gives me 50% duty cycle but still A2B PLL is not happy with the quality of the clock coming from Jetosn. See below the difference between Jetson and A2B master board clock:
BCLK: pink(A2B master board clock) blue (Jetson clock pin 12)
It’s not just the FS clock, also the Bit clock is not clean, too much oscillation. What are you trying to achieve looking at SS project for the A2B? I am using the same project for the A2B nodes while supplying clocks from a clean source(WDZ master board) and everything is fine.
Mixer control is available for configuring I2S as slave.
amixer -c APE cset name="I2S1 codec master mode" "cbm-cfm"
amixer -c APE cset name="I2S1 codec frame mode" "i2s" (use the mode relevant for your usecase)
