Board Delay Value

Our custom board is in the process of memory characterization. Below are my questions regarding to the Figure 15 in the Application Note of memory characterization.

  1. The $CLK and $CMD value in Figure 15 is much larger than the PCB delay we generated from Jetson TK1 layout file. For example, the $CLK board delay is about 235ps rather than 320.3ps. Which one is proper to fill in the cell for Jetson TK1?

  2. The value 350.1 ps is used for all $CMD signals in Figure 15. Would it be better if I input the real PCB delay value for each cell?

3)I have the same concern for data byte.


Please use the real PCB delay value for all.

Hi Jim, thanks for you reply.

Could you show me an example of board delay file for Jetson TK1? Thanks!

The file in \extras\GenBKV is OK as example.
If your board $CLK is 235ps, just put 235 in there, others also.

You can check the tBKV result in \extras\GenBKV\tBKV_RESULT, all parameters generate here can be tune by shmoo result.
So tBKV just generate a baseline to start the shmoo, final vaule need be optimized after full shmoo done.

If all cfg file you generate can pass sanity, then it’s a good base to start shmoo.
To be easy, if your board layout copy JTK1 or very close as JTK1, use JTK1 cfg start your shmoo also OK as long as it can pass sanity.