Our custom board is in the process of memory characterization. Below are my questions regarding to the Figure 15 in the Application Note of memory characterization.
The $CLK and $CMD value in Figure 15 is much larger than the PCB delay we generated from Jetson TK1 layout file. For example, the $CLK board delay is about 235ps rather than 320.3ps. Which one is proper to fill in the cell for Jetson TK1?
The value 350.1 ps is used for all $CMD signals in Figure 15. Would it be better if I input the real PCB delay value for each cell?
3)I have the same concern for data byte.