Required Info:
- Software Version
DRIVE OS 6.0.6 - Target OS
Linux - SDK Manager Version
1.9.2.10884 - Host Machine Version
native Ubuntu Linux 20.04 Host installed with DRIVE OS DOCKER Containers
Describe the bug
I found some conflicts in the official documentation about NvSciC2cPcie, both with hardware setup and data transfer.
Hope that these can be clarified in the forum.
hardware setup
in https://github.com/ZhenshengLee/nv_driveworks/blob/main/drive-agx-orin-doc/1-start-guide/DI-10587-003_v03.pdf
we can see that the pcie-cable should be linked like this, which means (Orin1) miniSAS port -A <–> (Orin2) miniSaS port -A
but in driveos doc site Chip to Chip Communication | NVIDIA Docs, we can see tha picture is like this, which means (Orin1) miniSAS port -A <–> (Orin2) miniSaS port -B
Question1: which one is correct to make NvSciC2cPcie communication work?
data transfer
in Chip to Chip Communication | NVIDIA Docs , we can see that the channel backend can be used for Root port and End point.
nvscic2c_pcie_s0_c5_{1, 12} is for Root Port, and nvscic2c_pcie_s0_c6_{1, 12} is for End Point,
but in cgf doc website, Compute Graph Framework SDK Reference: CGF Channel Sample
we can see
nvscic2c_pcie_s0_c5_{1, 12} is for End Point, and nvscic2c_pcie_s0_c6_{1, 12} is for Root Port,
Endpoints with c5 are end-port (EP) endpoints on the PCIe bus. Endpoints with c6 are toot-port (RP) endpoints on the PCIe bus. The EP and RP namings are for HW node identification, and do not signify direction of allowed data flows. Each pair of connected endpoints may transfer data in either direction. c6 is connected to Tegra A while c5 is connected to Tegra B.
Question2: which one is correct of the channel configuration?
Question3: how to check within the device if developers are using the wrong channel configuration?
Thanks.
