# Calculating/Getting register adresses of gpio pins **URL:** \ **Category:** Jetson AGX Orin\ **Tags:** gpio\ **Created:** [October 30, 2024, 8:01am UTC](https://forums.developer.nvidia.com/t/calculating-getting-register-adresses-of-gpio-pins/311661 "2024-10-30T08:01:24Z")\ **Posts on this page:** 12\ **Page:** 1
**Author:** ![jost38](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@jost38](https://forums.developer.nvidia.com/u/jost38)\ **Post date:** [October 30, 2024, 8:01am UTC](https://forums.developer.nvidia.com/t/calculating-getting-register-adresses-of-gpio-pins/311661/1 "2024-10-30T08:01:24Z")
Hello, I am currently using a Jetson AGX Orin devkit with Jetpack 5.1. At the moment, I control the GPIO Pins of the 40Pin header on the Devkit through the sysfiles with the GPIO numbers. But I would like to be able to modify the Pin behavior directly through their register addresses. Which I previously did on a Jetson Xavier NX, but I’m having trouble getting the addresses of the pins. Before, I converted the default dtsi files via the “pinmux-dts2cfg.py” script to a cfg file. In this, I could just read the register addresses for each pin and its control register. pinmux.0x022138e0 = 0x00000001; # CONFIG T7 pinmux.0x02431070 = 0x00000000; # GPIO dap5\_din\_pt7 (Without actually using/flashing the config) However, it seems converting dtsi files on AGX Orin is no longer possible/necessary. [In Orin pinmux python giving key error](https://forums.developer.nvidia.com/t/in-orin-pinmux-python-giving-key-error/234495) [Python pinmux-dts2cfg.py Error Processing GPIO File](https://forums.developer.nvidia.com/t/python-pinmux-dts2cfg-py-error-processing-gpio-file/251146) I can calculate the Control register address of a pin with the DRM of the Orin: [https://docs.nvidia.com/jetson/archives/r35.1/DeveloperGuide/text/HR/JetsonModuleAdaptationAndBringUp/JetsonAgxOrinSeries.html#mb2-configuration-changes](https://docs.nvidia.com/jetson/archives/r35.1/DeveloperGuide/text/HR/JetsonModuleAdaptationAndBringUp/JetsonAgxOrinSeries.html#mb2-configuration-changes) But I’m not sure how I can get the address of the gpio value. Any way of easily obtaining those? ---
**Author:** ![carolyuu](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/carolyuu/32/14043_2.png) [@carolyuu](https://forums.developer.nvidia.com/u/carolyuu)\ **Post date:** [October 30, 2024, 8:30am UTC](https://forums.developer.nvidia.com/t/calculating-getting-register-adresses-of-gpio-pins/311661/2 "2024-10-30T08:30:13Z")
Hi, If you are designing a custom base board, then it means some adaptation configurations are needed. Otherwise, your board may not work fine. For Orin AGX series, you could refer to below document [https://docs.nvidia.com/jetson/archives/r36.3/DeveloperGuide/HR/JetsonModuleAdaptationAndBringUp/JetsonAgxOrinSeries.html?highlight=universal%20serial%20bus#jetson-agx-orin-platform-adaptation-and-bring-up](https://docs.nvidia.com/jetson/archives/r36.3/DeveloperGuide/HR/JetsonModuleAdaptationAndBringUp/JetsonAgxOrinSeries.html?highlight=universal%20serial%20bus#jetson-agx-orin-platform-adaptation-and-bring-up) (please be aware that above link is for rel-36.3/jetpack6.0) This document includes below configuration 1. pinmux change & GPIO configuration 2. EEPROM change as most custom boards do not have an EEPROM on it. 3. Kernel porting 4. PCIe configuration 5. USB configuration 6. MGBE configuration 7. RGMII configuration Thanks! ---
**Author:** ![jost38](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@jost38](https://forums.developer.nvidia.com/u/jost38)\ **Post date:** [October 30, 2024, 8:35am UTC](https://forums.developer.nvidia.com/t/calculating-getting-register-adresses-of-gpio-pins/311661/3 "2024-10-30T08:35:58Z")
For now I’m just using the Devkit and wish to control the Gpio-Pins on the 40Pin Header directly though their register address, for a lower and more consistent latency. ---
**Author:** ![jost38](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@jost38](https://forums.developer.nvidia.com/u/jost38)\ **Post date:** [October 30, 2024, 2:18pm UTC](https://forums.developer.nvidia.com/t/calculating-getting-register-adresses-of-gpio-pins/311661/4 "2024-10-30T14:18:10Z")
The linked article has basically the same information as the one I linked. And I can’t find a way there to get the register address of the value for the gpio pin. Is there anywhere the registers are stored, like they were in the now obsolete cfg file generated by the python script. Where I could cat for the specific gpio I’m looking for. Or at least a way to calculate the address similar to the cfg register address of the pin. ---
**Author:** ![KevinFFF](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/kevinfff/32/15508_2.png) [@KevinFFF](https://forums.developer.nvidia.com/u/KevinFFF)\ **Post date:** [November 1, 2024, 2:27am UTC](https://forums.developer.nvidia.com/t/calculating-getting-register-adresses-of-gpio-pins/311661/6 "2024-11-01T02:27:26Z")
Hi jost38, We would suggest you updating to the latest JP5.1.4(R35.6.0) to verify. To get the pinmux register for specific pin, you can refer to the Orin TRM document. And run the following command to get its value. ```auto $ sudo busybox devmem ``` ---
**Author:** ![jost38](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@jost38](https://forums.developer.nvidia.com/u/jost38)\ **Post date:** [November 5, 2024, 8:18am UTC](https://forums.developer.nvidia.com/t/calculating-getting-register-adresses-of-gpio-pins/311661/7 "2024-11-05T08:18:02Z")
Hi, so I have worked through the TRM. This is the way I found of calculating the correct registers: * * * PIN 7 on Orin AGX Find the Pin in the Pinmux excel sheet through Signalname from DevKitCarrierBoardSpecification → PIN7 MCLK05 L57 (Carrier Board Speci) =\> L57 MCLK05 SOC\_GPIO33 GPIO3\_PQ.06 (Excel Pinmux) PADCTL: 1. search for “SOC\_GPIO33” in TRM -\>found in SystemCPomponents-\>MultipurposeIO-\>G3 Pad Control Registers :PADCTL\_G3\_SOC\_GPIO33\_0 :Offset: 0x70 :And Bit Description 2. Find Base adress Block From Table 8.4.1.6 Pad Control Grouping find corresponding Base Address Block -\>G3 Yes PADCTL\_A0 3. FInd Base Adress In Table 3.2.2 System Adress Map -\>PADCTL\_A0 0x02430000 0x02430fff SYSTEM 4. Combine Base and Offset 0x02430000 + 0x70 = 0x02430070 5. Bit description 12 E\_SCHMT 0=Disable 1=Enable 10 GPIO\_SF\_SEL 0=GPIO 1=SFIO 8 E\_LPDR 0=Disable 1=Enable 7 E\_LPBK 0=Disable 1=Enable 6 E\_INPUT 0=Disable 1=Enable 5 E\_IO\_HV 0=Disable 1=Enable 4 TRISTATE 0=Disable 1=Enable 3:2 PUPD 0=None 1=PullDown 2=PullUp 3=RSVD 1:0 PM 0=RSVD0 1=EXTPERIPH4 2=DCB 3=RSVD3 6. Usage Set GPIO: Bit 10 = 0. For the output, set Bit 4 = 0 ; Bit 6 = 0. For Input, set Bit 4 = 1 ; Bit 6 = 1. GPIO Control Register 1. Identify GPIO Port and Number Port:Q Pin:6 2. Find corresponding GPIO controller -\>From Table in Chapter 8.5.1.2 Features GPIO Controllers and Port Mapping GPIO\_CTL2 M (8) N (8) EDP VDDIO\_EDP P (8) Q (8) R (6) G3 3. Find Base Adress of controller -\>In GPIO\_CTL2\_GPIO0 0x02230000 0x02230fff SYSTEM =\>IS GPIO\_CTL2\_GPIO0 CORRECT HERE AND WHY GPIO0 ? 1. Find Adresses of the Registers with Port(q) and Pin(6) -\>In 8.5.6 GPIO Control Registers GPIO\_Q\_ENABLE\_CONFIG\_06\_0 Offset: 0x126c0 GPIO\_Q\_DEBOUNCE\_THRESHOLD\_06\_0 Offset: 0x126c4 GPIO\_Q\_INPUT\_06\_0 Offset: 0x126c8 GPIO\_Q\_OUTPUT\_CONTROL\_06\_0 Offset: 0x126cc GPIO\_Q\_OUTPUT\_VALUE\_06\_0 Offset: 0x126d0 GPIO\_Q\_INTERRUPT\_CLEAR\_06\_0 Offset: 0x126d4 (GPIO\_Q\_INTERRUPT\_STATUS\_G6\_0 Offset: 0x12718) =\> as seen the other Offsets als always constant from the first and a fixed value can be added 1. Combine Base and Offset Address 0x02230000 + 0x126c0 = 0x022426c0 for ENABLE\_CONFIG of pin pq.06 ? 2. Bit description ENABLE\_CONFIG: 7 TIMESTAMPING\_FUNCTION 0=Disable 1=Enable 6 INTERRUPT\_FUNCTION 0=Disable 1=Enable 5 DEBOUNCE\_FUNCTION 0=Disable 1=Enable 4 TRIGGER\_LEVEL When NO TRIGGER: this field is irrelevant When LEVEL: 0 = Trigger on level Low. 1 = Trigger on Level High When SINGLE EDGE: 0 = Trigger on Falling Edge. 1 = Trigger on Raising Edge When BOTH EDGES: this field is irrelevant 3:2 TRIGGER\_TYPE 0=NO\_TRIGGER 1=LEVEL 2=SINGLE\_EDGE 3=DOUBLE\_EDGE 1 IN\_OUT 0=In 1=Out 0 GPIO\_ENABLE 0=Disable 1=Enable * * * However, I am unsure as to which the correct Base address of the GPIO controller would be. Is it GPIO\_CTL2\_GPIO0 and why is it the one with the zero at the end? Are the adresses for the pin pq.06 correct? PADCTL = 0x02430070 GPIO\_CTL = 0x022426c0 (for enable config) This is regarding the Jetson Orin AGX. For the Jetson Xavier Nx I’m unable to locate the System Address Map for the GPIO controller in the Xavier NX TRM. With is present in the Orin Series TRM in Chapter 8.5.3.1 System Address Map (AMAP). Can you also assist me in locating that for the jetson Xavier series. ---
**Author:** ![KevinFFF](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/kevinfff/32/15508_2.png) [@KevinFFF](https://forums.developer.nvidia.com/u/KevinFFF)\ **Post date:** [November 6, 2024, 8:32am UTC](https://forums.developer.nvidia.com/t/calculating-getting-register-adresses-of-gpio-pins/311661/8 "2024-11-06T08:32:41Z")
> [@jost38](#): > > Are the adresses for the pin pq.06 correct? > PADCTL = 0x02430070 Correct! > [@jost38](#): > > Can you also assist me in locating that for the jetson Xavier series. Please open another topic for Xavier since the current topic is in AGX Orin category. ---
**Author:** ![jost38](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@jost38](https://forums.developer.nvidia.com/u/jost38)\ **Post date:** [November 6, 2024, 9:23am UTC](https://forums.developer.nvidia.com/t/calculating-getting-register-adresses-of-gpio-pins/311661/9 "2024-11-06T09:23:35Z")
Thank you for the confirmation. Can you still explain why GPIO\_CTL2\_GPIOzero is the correct base address? Respectively if it is always GPIO\_CTLx\_GPIO0 (GPIOzero) and what the other GPIO\_CTLx\_GPIOy meaning/purpose is. ---
**Author:** ![KevinFFF](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/kevinfff/32/15508_2.png) [@KevinFFF](https://forums.developer.nvidia.com/u/KevinFFF)\ **Post date:** [November 14, 2024, 6:35am UTC](https://forums.developer.nvidia.com/t/calculating-getting-register-adresses-of-gpio-pins/311661/10 "2024-11-14T06:35:38Z")
> [@KevinFFF](#): > > Correct! Correct is for PADCTL register of `PQ.06` ![image](https://global.discourse-cdn.com/nvidia/original/4X/7/b/a/7ba079828ac2581838bc580f52df539229fc723b.png) Please refer to the above info from TRM that all control registers use the same base address of GPIO\_CTL as following. ![image](https://global.discourse-cdn.com/nvidia/optimized/4X/4/8/c/48cd4ad760efbaa7f003c6ff5d0d9c8d178cbb38_2_690x27.png) ![image](https://global.discourse-cdn.com/nvidia/original/4X/f/6/1/f617da2501c7597200775ce33fb153f479cea259.png) So, please use 0x02200000(GPIO\_CTL) + 0x126c0(GPIO\_Q\_ENABLE\_CONFIG\_06\_0) = **0x022126c0** for `ENABLE_CONFIG` of **PQ.06** Please try to control it and check if the pin state would be changed. ---
**Author:** ![jost38](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@jost38](https://forums.developer.nvidia.com/u/jost38)\ **Post date:** [November 14, 2024, 8:26am UTC](https://forums.developer.nvidia.com/t/calculating-getting-register-adresses-of-gpio-pins/311661/11 "2024-11-14T08:26:38Z")
Ah ok, thank you. I confirmed that it works with busybox and can control/read the pin. ---
**Author:** ![jost38](https://developer.download.nvidia.com/images/forums/profile-default-devtalk-84.png) [@jost38](https://forums.developer.nvidia.com/u/jost38)\ **Post date:** [November 21, 2024, 11:47am UTC](https://forums.developer.nvidia.com/t/calculating-getting-register-adresses-of-gpio-pins/311661/13 "2024-11-21T11:47:00Z")
I just realized that PIN16 of the 40Pin expansion header is part of the AON Group, with it being GPIO3\_PBB.0. And for them the TRM mentions: > All AON, i.e. GPIO\_, Control Registers share the same base address under the name AON\_GPIO\_0, > where = AA, BB, CC, DD, EE, and GG. Basically the same as for the Non AON Control Registers. However, I am unable to find the base Address of the AON GPIO Control Register (AON\_GPIO\_0) in the Address Map of the TRM, as mentioned right below: > For the base address of Non-AON GPIO Control Registers (GPIO\_CTL) and AON GPIO Control Registers (AON\_GPIO\_0), please refer to the System Address Map in this TRM. As there seems to no AON\_GPIO\_0 mentioned in the System Address map. But I found in a git repo (jetGpio) the base Address of AON\_GPIO\_0 to be 0x0c2f0000. Which worked for reading the values of a pin when added with its offset. But I am not able to find that information in the TRM. ---
**Author:** ![system](https://sea2.discourse-cdn.com/nvidia/user_avatar/forums.developer.nvidia.com/system/32/68080_2.png) [@system](https://forums.developer.nvidia.com/u/system)\ **Post date:** [December 5, 2024, 11:47am UTC](https://forums.developer.nvidia.com/t/calculating-getting-register-adresses-of-gpio-pins/311661/14 "2024-12-05T11:47:09Z")
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